[Technology Report]
PCI Express Design: A Lesson In Techno-Shock
Start the coffee. Embedded designers are in for the long haul when it comes to implementing PCI Express, but the rewards are worth it.
Start the coffee. Embedded designers are in for the long haul when it comes to implementing PCI Express, but the rewards are worth it.
Parallel PCI and PCI-X, hampered by its wide bus that makes layout difficult, no longer is the speed champ. Winning with a technical knockout of performance and new chips is... PCI Express. But will dealing with this high-speed serial technology be easier or harder?
PCI Express looks like the holy grail (Fig. 1). Compared to PCI/PCI-X, it is fast. It uses fewer pins, has more features, and offers backward-compatibility with PCI/PCI-X software.
So what's the problem? Generally, many designers are simply ill-prepared for PCI Express' quantum leap in board and system design technology. Embedded designers will find that its 2.5-GHz speed is a major problem—it's almost two orders of magnitude different from what they're accustomed to. (PCI tops out at 133 MHz.) In addition, routing and power issues persist. Furthermore, analog designers will have to meet new, more restrictive requirements.
This leaves two alternatives: Buy something, or bite the bullet and learn how to design to the new standard. The former is what most PCI Express systems employ now. Motherboards feature PCI Express sockets. And PCI Express cards are readily available, though the number of choices is limited but growing. Thus, system designers can simply select products, plug a system together, and get a working final product. Such support also will be needed for Advanced Switching, PCI Express' sibling (see "Advanced Switching Waits In The Wings," p. 60).
The other alternative is the more arduous route—engineers designing boards to plug into a PCI Express motherboard or designing custom embedded systems. To alleviate part of the problem, one could use modules like those based on COM (computer on module) Express. Kontron, PFU Systems, and Radisys are three companies that provide COM Express modules complete with processors, Gigabit Ethernet, and, of course, PCI Express (Fig. 2).
Next, developers must build a carrier board that links the modules to PCI Express devices on the carrier board, thereby cutting the design problem in two. Either way, a knowledge of PCI Express is needed, which means comprehending very high-speed analog design.
Power and clock distribution, less critical aspects of PCI and PCI-X system design, have become quite significant. Systems that could be built on four-layer boards now require eight-layer boards with multiple ground and power planes.
The PCI Special Interest Group (SIG) is responsible for the PCI Express specification. The SIG also is a source of information for PCI Express designs. (Some information is available only to members). Specifications address all aspects of PCI Express, from the physical design (even including connectors and cabling details) to the wire protocol. On top of that, PCI Express design recommendations can be beneficial to designers.
Design-related documents that cover jitter modeling and bit error rate (BER) also come in handy. The amount of jitter determines how well devices will interoperate. PCI depends more on clock skew, while PCI Express is affected more by jitter because the clock is embedded in the data (Fig. 3).
PCI Express utilizes a 100-MHz clock and generates the 2.5-GHz serial stream via a phase-lock loop (PLL) (Fig. 4). The quality of the serializer/deserializer (SERDES) is key to a PCI Express system's success. However, it will only be as good as the transmission line between the transmitter and receiver. Tolerances on the circuit board between two PCI Express devices are critical.
Tom Tinory, StarGen's director of Board Product Development, notes that the design of power planes supporting PCI Express devices can be tricky and complex. Regulated power must be supplied equally to these devices for the SERDES, receiver termination, and the analog voltage when driving the PLL. It may be possible to "carve" these power-plane splits onto a single power plane. But in many cases, there's a need for two or three planes.
PCI Express electrical design rules require high-speed differential signals to be surrounded by ground above and below. Combining this rule with the complexity of power-plane splits drives up the number of layers required for electrically clean and compliant designs.
PCI EXPRESS SERDES High-speed SERDES designs aren't new, but they have been found in devices like FPGAs from Altera and Xilinx. They also show up in Gigabit Ethernet designs. This gives companies working in these areas a head start in dealing with the SERDES design complexities.
"Designers need to do their homework before they start," says Jean-Marc Patenaude, director of Logic Platform Solutions for Rambus. "They should not assume they can do it all themselves."
Patenaude knows about supporting the client and about high-speed SERDES. Rambus developed a seven-step support process along with signal-integrity analysis software. The company's SERDES design incorporates more testability features, such as ac JTAG testing, compared to the standard JTAG support. The ac tests can check on bit-error-rate (BER) eye diagram data.
Rambus isn't alone in this effort. Companies such as Mentor Graphics and Synopsys provide similar services. Even companies like LSI Logic are getting involved in their clients' board designs.
LSI Logic retains a good deal of SERDES expertise from its Fibre Channel work. Serial ATA (SATA) and Serial Attached SCSI (SAS) are two new, high-speed serial interfaces that LSI Logic is melding with PCI Express. Harmel Sangha, LSI Logic's director of CoreWareIP Marketing, noted that the company also created its own package model and Spice interface design tools to check signal integrity in high-speed designs. This is important in an environment that may have as many as 64 SERDES.
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