[Technology Report]
Mobile Storage: Chips Served With Hard-Disk Salsa
Tiny hard isks and massive flash memory devices give designers a spicy array of storage choices.
Tiny hard disks and massive flash memory devices give designers a spicy array of storage choices.
"We want more storage!" it's the hue and cry heard from designers of portable devices. Flash memory and compact hard drives help meet that need with ever-larger capacities.
Flash memory is the low-power winner, but hard drives have the edge when it comes to capacity. Both have changed the way mobile devices are designed. They also have driven the growth of scores of devices, from cell phones to digital cameras to MP3 players.
Removable flash memory comes in a range of form factors, like those from SanDisk (Fig. 1). Commonly available products include Compact Flash, MultiMedia Card, Memory Stick, SD (secure digital), miniSD, SmartMedia, and xD-Picture.
Many cell phones have the Subscriber Identity Module (SIM). Although SIM cards typically use EEPROM, they're turning to flash as storage requirements grow. Kingston's DataTraveler II+ is an example of the USB flash memory drive (Fig. 2). PCMCIA storage cards are also available. In the next few years, however, ExpressCard likely will replace PCMCIA and give USB flash-memory drives a run for their money (see "ExpressCard Replaces PCMCIA," p. 69).
Non-removable storage uses the same technology as its removable counterpart. Non-removable storage tends to be found in devices like cell phones and MP3 players, where size is critical and a removable device slot takes up too much space.
Not all flash memory is alike. Flash arrays come with and without controllers. For example, Compact Flash contains a circuitry interface between the flash array and the outside world, unlike SmartMedia. The other choice is between NAND or NOR flash-memory technologies.
NOR flash started out in front because of its memory-style interface. It also had a faster read access time than NAND flash. This made NOR ideal for applications, because they could be executed in place (XIP). But beware of NOR's downsides. For instance, it takes longer to reprogram NOR flash than NAND. This isn't as important for applications that are rarely written, but it becomes an issue for data storage that changes more often. Also, when it comes to the number of erase cycles, NOR flash has a lower limit compared to NAND by a factor of 10. NOR erase cycles are on the order of 10k to 100k, which is more than enough for many applications, but definitely not for all.
NAND implementations required the application code to be copied to RAM first. Single-chip solutions like M-Systems' DiskOnChip combine NAND flash and SRAM to get the capacity of NAND and the flexibility of NOR (Fig. 3). This is one reason why NAND is gaining steam in new applications.
The DiskOnChip also adds an intelligent front end that hides the internal mapping of logical blocks to physical flash blocks to implement a wear-leveling algorithm. This is important because typically a flash chip is useless if one of its blocks wears out. For instance, if periodically changing data is stored in the first logical block 10 times as often as the other blocks change, then the life of the chip will be based on the use of the first block. Wear leveling essentially employs the least-used block for the next update. It takes a little juggling to move blocks around and keep track of what will be used next, but this is transparent to the host.
NAND also can erase smaller blocks, but this tends to be less of an issue for block-oriented storage devices. Byte-level erasures are usually more important in flash microcontrollers that utilize flash for nonvolatile data storage or for making minor changes to an application. It can make a difference in storage applications if data is packed in very small blocks.
Both NAND and NOR technologies encounter the problem of bit flipping, where data changes inadvertently. It's not all that common, but it occurs more with NAND. Error-detection/error-correction (EDC/ECC) bits enable access algorithms to detect errors, which also is more likely to happen with NAND devices. It can be implemented by the host as well, but intelligent flash memory can make this feature operate transparently.
Large arrays of anything tend to raise the probability of problems with one or more blocks. A host can handle bad block remapping or, again, an intelligent flash device can handle this transparently. A hard disk typically works this way, too.
The importance of handling errors is usually based on the type of data. Application code needs very reliable storage, whereas a few errors in multimedia data often will go unnoticed as the problems occur for only a fraction of a second.
In addition, NAND holds the edge when it comes to price and capacity. The 2-Gbyte USB flash drives are NAND-based. NOR is smaller by a factor of eight. NAND also costs less, even when adding in front-end logic to make the NAND flash easier to use.
Developers tend to prefer single-chip solutions whenever possible. At this point, high-end NOR flash capacities are on the order of 512 Mbytes. NOR also dominates many handheld devices like cell phones. Likewise, NOR developers such as Intel, AMD, and Fujitsu are pushing NOR capacity with multiple bits per cell and low-power, 1.8-V operation. Intel's StrataFlash Multi-Level Cell technology delivers two bits per cell.
Embedded developers need to talk with a range of vendors to find the best fit for their application. Flash vendors tend to use one technology, and their solution won't always match your design requirements. In many instances, rotating magnetic media may better meet capacity requirements.
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