The phrase "high-speed digital" evolved during the time of vacuum tubes and early digital computers.1 Ever since, the driving need for better system performance and higher clock speeds has presented greater challenges to designers. Those challenges became even more formidable when integrated circuits entered the picture.
When Jack Kilby and Robert Noyce invented the silicon IC in 1959, they introduced a whole new challenge—high functional integration in a compact space that wasn't possible with prior tube and discrete transistor designs. As clock frequencies elevated into the tens and then hundreds of megahertz, problems like ringing and terminations, drive levels, and interference between signals became day-to-day concerns.
Eventually, analyzing and resolving these problems came to be known as signal integrity. This discipline set out to meet the formidable task of getting data between two functional blocks while attaining the error performance required by the overall system.
In recent years, Moore's Law has taken over as a driving force in the computing industry, pushing clock rates into the gigahertz region. The design challenges for traditional parallel data-transfer buses with enough capacity and stability for use with such high-performance processing became so severe that a new approach was adopted—serialization.
Even though the data rates associated with a serial approach are much higher (multi-gigabit-per-second rates are common), serial buses offer the ability to control a single-channel signal environment while preventing many of the major problems associated with parallel buses. Numerous standards now exist for such links, including InfiniBand, Serial ATA, USB 2.0, PCI Express, Fibre Channel, RapidIO, and HyperTransport.
Yet high-speed serial data links do produce a set of their own design problems. In particular, there's the integration of a number of discrete designs across many engineering specialties that must come together to make a functional system. Fortunately, a new method is available for high-speed, serial-data-link design and integration.
DESIGN CONSIDERATIONS
Each of the functions and interconnections of a serial data link represents a design activity. Consider the profile of a typical link (Fig. 1).
Signal Processing—Pattern Generator/Encoder/Equalizer/ Decoder: DSP designers work with the system's signal-processing functions. On the transmitter (TX) side, the incoming data is formatted and encoded for transportation across the physical layer (PHY) according to a specification (either standard-based, such as 8B/10B, or proprietary). On the receiver (RX) side, the incoming data is sampled, equalized, and decoded before being passed on to the next layer.
EDA: Designers of these functions often use language-based tools such as Matlab or C++ for algorithmic design, then proceed to HDL synthesis and functional verification. Subsequently, this HDL code is used as input to the ASIC production process.
Challenge: One of the major obstacles of this design task is to ensure that the real-world effects from the rest of the channel are adequately modeled during the design process.
Analog IC—Pre-And De-Emphasis/Driver/Receiver: Designing the line driver and receiver functions, which may include signal emphasis, usually is carried out in a mainstream analog IC design flow. Some form of Spice simulator is the primary circuit-level design tool.
EDA: Designers of leading-edge systems either work with discrete transistors or low-level cells to create the necessary functions. Design information can exist in many forms, depending on the user. The IC fabrication process will use a netlist of the design to manufacture the circuits. End users of an IC also may receive this information if they're " inhouse." External customers wishing to use a catalog IC often will receive information either in a proprietary encrypted file format or as an open-source standard, such as IBIS or Verilog-A.
Challenge: The TX and RX designs are generally carried out with typical waveforms and worst-case loads to meet an interface standard or waveform performance, rather than in the context of an overall system.
Packaging—TX/RX Packages: Package design can be carried out by specialist packaging companies or in larger companies by in-house designers.
EDA: Design tools are typically EMbased using either full 3D or 3D planar methods. Although such tools have been memory-limited when modeling larger packages, smart processing of layout information can greatly reduce processing size, and recent advances now provide much greater flexibility.2 Information for manufacture is geometry-and materials-based. EM design tools also can be used to produce working simulation models of packages for IC designers. Options include multiport S-parameters and equivalent circuit models.
Challenge: Though equivalent models are often preferred because of their inherent compatibility with Spice, equivalent network synthesis will almost always leave the model with limited accuracy. In some cases, the resulting circuit can have thousands of components. S-parameters, though, contain all of the necessary information but can't be directly handled by conventional Spice simulators, especially as the number of ports grows.
Board—Daughtercards/Backplane/ Motherboard: Board design is perhaps the most challenging aspect of modern links. A board's interconnect design can make or break system performance. Designers typically don't have the luxury of carrying only one signal path (sometimes referred to as a "lane") on a given board.
Multiple signal paths can lead to less than ideal routing through various layers, putting them in close proximity to interfering or aggressor signal paths. A number of isolation techniques could be used, such as via fences and dedicated ground planes, but they're expensive in terms of real estate and can't always be accommodated.
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