If you're designing a circuit in a high-level design language like Verilog or VHDL, there are a few simple rules to follow to ensure the synthesizer generates the intended circuit.
First, avoid using both positive and negative edge-triggered flip-flops for the same clock signal. Triggering flip-flops off different edges of the same clock likely will result in one or more inverters being introduced into the clock path. This normally will cause an unwanted skew in the clock signal.
Second, always specify all logic conditions explicitly or use a default assignment. The most common mistake is to specify an IF-THEN statement with no ELSE when designing a multiplexer. Frequently, this will be interpreted as a level-sensitive latch. A similar mistake often is made with case statements where one specific case is forgotten or the default case is not specified.
Third, watch out for multiple assignments to the same variable. Typically, the cause of this might be a simple copy and paste of code where the variable name change was forgotten. If the synthesis engine even allows this type of error, you can be sure the results will be undesirable.
Note that most HDL design tools would provide warnings for the above issues, which is why they should never be turned off or ignored. Keep your compiler and synthesis tool happy, and you will be happy.
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