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[POV: Point Of View]
FPGAs: Architectural Innovations Open Up New Applications

Dennis Kish  |   ED Online ID #13543  |   October 12, 2006


FPGAs have always offered fast turnaround and on-the-fly reconfigurability, but at a higher unit cost. ASICs have promised a lower unit cost at high volumes, but only if designers can afford the time and high non-recurring engineering (NRE) costs associated with developing a custom IC.

Traditionally, designers have selected FPGAs for lower-volume applications where the market demands a high degree of reprogrammability or quick time-to-market and where cost usually isn't a differentiating factor. They have opted for ASICs where very high-end product volumes have let them amortize their NRE costs and take advantage of lower per-unit pricing.

But the overall trend in the market continues to march toward programmable solutions. Gartner calculates the FPGA market reached $3.26 billion in 2005. By 2010, the same analysts predict it will more than double to $6.72 billion.

NEW MARKETS
More importantly, the FPGA market is rapidly expanding into new market segments. Over the last decade, communications and data-processing applications have dominated FPGA use.

In 2005, for instance, those two market segments represented approximately 59% of all FPGA shipments. Five years later, Gartner analysts expect those two market segments to drop to 45% of the total FPGA market as designers in traditional ASIC arenas such as consumer, industrial, and automotive shift to programmable alternatives.

The recent architectural evolution of programmable solutions is largely driving this growth. Designers in these markets are looking for viable ASIC alternatives. They need a single-chip solution that uses a highly efficient architecture capable of integrating basic system functions at low cost while consuming minimal power. They also need a platform that will let them maximize functional integration without risking the large upfront investment associated with the development of a full-custom ASIC.

Over the last few years, FPGA vendors have brought to market new architectures that meet all these requirements. Vendors now support their latest programmable fabrics with a wide array of fixed functions. These new FPGA architectures not only offer traditional processor and interface blocks, but they also can add mixed-signal capabilities. Suddenly, the value proposition that ASICs have long claimed—the ability to collapse major systems functions into a single chip—is now available in FPGAs as well.

Moreover, the ability to offer these key functions in a highly programmable fabric backed by a comprehensive, low-cost development tool environment offers an extremely attractive value proposition. In the automotive arena, where design cycles can extend for many years, the ability to combine microcontroller and mixed-signal function blocks with programmable logic enables designers to quickly and easily modify their designs.

LOW-POWER ADVANCES
One of the major liabilities to using FPGAs in consumer applications has been power consumption. Features inherent in programmable logic have made it difficult for FPGA suppliers to offer low-power options. That limitation, in turn, has restricted the utility of FPGAs in many portable consumer applications.

But the recent development of flash memory-based programmable logic architectures and the continual optimization of circuit designs are quickly eliminating that distinction. In the near future, designers can expect to see flash-based FPGAs that consume less than 5 µW of standby current.

As the industry advances further down the deep-submicron-process track, the costs associated with IC development, engineering resources, IP, and mask sets will continue to rise. While design teams need to leverage the area advantages of leading-edge process technologies, they often can't afford the risks associated with a full custom device. Today's programmable logic technologies offer designers in a growing variety of applications the opportunity to achieve their design goals while mitigating that risk.

See associated figure


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