The heat is on for designers. Whether crafting nanoscale packages or giant supercomputers, today's engineers are under increasing pressure to get the heat out of their ever-higher-octane designs. To do this, designers look to solutions that include new materials with better thermal interfaces, innovative cooling techniques, better packaging approaches, and smarter design layouts using advanced thermal-management EDA tools.
Since its inception, the electronics industry has chanted the smaller, faster, cheaper mantra. Thanks to advanced photolithographic and other manufacturing techniques, designers can continually push the limits of miniaturization. But heat remains an obstacle. As a result, new thermal-management techniques must be developed for further progress to be made.
Many efforts are under way to address the heat obstacle, including mechanical, chemical, and metallurgical technology research, as well as electronics engineering. Designers are working to improve heatsinks, fans, and liquid cooling.
Better heatsinks facilitate the flow of heat to the ambient air. Thermal vias enhance the thicknesses of package laminates and pc boards. Thicker power and ground planes are appearing on pc boards. Microchannel liquid-cooling techniques use convection and conduction methods alike. EDA software is becoming more integral to a chip's design, packaging, and placement within a larger system as well (see "Software Lends A Helping Hand" at www.electronicdesign.com, ED Online 13611).
Meanwhile, packages are using heat slugs to stay cool. Some packages feature efficient decoupling of electrical and thermal characteristics. And in addition to conduction and convection, radiation has become another option for heat removal.
One thorny problem these days involves hotspots on ever-denser chips, reducing IC reliability levels. As a result, minimizing the thermal stress of ICs at the die level is becoming critical. In advanced microprocessors and power ICs, power-dissipation levels have reached 100 W and higher, calling for sophisticated heat-management techniques.
The hotspot problem mainly exists in high-performance microprocessors, advanced graphics processors, and other high-end chips that pack the maximum performance in the smallest space. These devices are being made at very small geometries with line widths as low as 90 nm and even 65 nm. In the future, other commodity chips will be made at geometries of 45 nm and smaller and will face the same hotspot problems that we face today.
"Hotspot migration will move to center stage as one of the major design objectives in a wide variety of chips, including CPUs, graphics chips, communications devices, LEDs, and optical chips," says Jesko von Windheim, chief executive officer of Nextreme Thermal Solutions. "This problem has only started to be acknowledged, and we expect it to become more pervasive over the next year."
Designers deal with most of these hotspot problems by using large (compared to the chip they're cooling) and cumbersome cooling systems. This ultimately compromises the small size designers are looking for in a packaged chip.
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Packaging also plays an important role in heat management. The latest trend is to reduce the number and lengths of interconnects within a chip or chips on a board, solving noise and heat generation at the same time. This is particularly challenging when packaging a low-power logic chip with high-power CPUs.
One approach is the side-by-side flip-chip packaging developed by NEC Electronics America for high-speed and large-memory applications such as cell phones, digital cameras, PCs, and video games. This method enables designers to pack up to eight memory chips and one logic chip, each with die dimensions of 17.3 by 17.3 mm, into a single ball-grid-array (BGA) package.
NEC recently developed a prototype package for interchip wideband data transfers that minimizes communications latencies and heat dissipation between interconnects. Known as SMAFTI (SMArt chip connection with FeedThrough Interposer), it will be in production by next year (Fig. 1).
One liquid-loop cooling technique developed by Advanced Thermal Solutions is used in an active BGA package. A forced heat spreader combines micro and mini channels in a resin package bonded directly to the die (Fig. 2, left). Fluid flow inside the channels is 0.5 to 1 L/minute. Within the spreader is an integrated pump that's deployed inside and outside the package, depending on the application (Fig. 2, right).
Regardless of the type of package, leakage power between silicon and its interconnects is a serious problem, one that's sure to worsen as device geometries shrink. "On a typical microprocessor, the CPU core dissipates a lot of power while the cache memory dissipates less power, leading to thermal mismatches," says Robert B. Conner, VP of marketing and business development at Nextreme Thermal Solutions. "This problem is multiplied by the use of multiprocessor cores on a chip."
Nextreme recently showed off an elegant, simple, and cost-effective solution. The company's lightweight and tiny " confetti" type bismuth-telluride thermoelectric microcooler material can be attached to the back of a chip, much like a piece of adhesive tape. The embedded thin-film material doesn't make noise like a fan in a cooling system, nor does it have any moving parts (Fig. 3).
The microcooler is mounted on the back of an IC package or chip by sputtering during the back end of an IC process. Nextreme is careful to point out, though, that it's collaborating with major semiconductor IC manufacturers at the moment—the technology remains two to three years away from full-scale production.
Proper packaging of discrete power devices like MOSFETs also can go a long way when it comes to good thermal management. On International Rectifier's DirectFET package, for example, the MOSFET is mounted to a pc board with a thin filler and heatsink attached (Fig. 4).
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