FPGAs are complex beasts these days, and the once trivial task of assigning signals to pins can be complicated and iterative. These guidelines for assigning signals to multipurpose pins force you to think about your signal assignments up front and reduce the chance of iterations based on a most-to least-constrained signal assignment process.
One assumption that has been made here is that you have identified a target device family and part based on the approximate size of your design and your signaling requirements. For each of these steps, always consider differential pair signals before single-ended signals.
First, assign specialized signals that only work on specific pins. Normally, this would be serial I/O signals and global clock signals. Second, assign large and/or high-speed signal busses, especially those that would be spread across more than one bank or region. If your busses require local clocking, consider banks or regions with more local clock-capable pins and assign the local clocks first.
If you're using more than one I/O standard for the FPGA device, you must also consider mapping out the I/O signaling to bank/region before getting started. This step alone requires special consideration since many I/O standards and voltage references are incompatible. Some I/O standards require voltage reference inputs on specific pins, making those pins unavailable for general use. Spread your high-speed output and bi-directional signals out somewhat to avoid simultaneous switching output noise (SSO) issues (see "Digital Design Tip: Avoid Clusters Of High-Frequency Outputs" at www.electronicdesign.com, ED Online 13089).
Third, slower and less constrained busses come next using the same basic principles in the second step, but with less emphasis on things like SSO. Fourth, individual signals normally should be done last. If you only have a few pins remaining or you run out of pins during your first iteration, consider moving to the device with the next higher I/O count, as marketing is sure to add some last-minute features, and you really don't want to go through this process again toward the end of the design cycle.
At each step, consider setting up a constraint file with the proper signal assignments and I/O standards, as well as an HDL file with the I/O portion of your design. Then, run your design through to place and route, because it's better to catch errors while moving from most-to least-constrained signals.
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