I can't believe it took me so long to write this column. I designed some good, low-frequency phase-locked loops (PLLs) about 33 years ago and wrote them up but never got it published. When I moved from Philbrick to National 30 years ago, I got some good voltage-to-frequency converters going, using the new LM331. I also wrote application note AN-210 (still in print) about 1978, which you can see at www.national.com/an/AN/AN-210.pdf.
I had a 10-kHz voltage-to-frequency converter. Testing it was a slow process, as the test technician had to trim the frequency to 20.0 Hz at 20.0 mV of VIN. He also also had to trim to 10,000.0 Hz at 10,000.0 mV, using coarse, medium, and fine trim pots. By multiplying the 20 Hz by a factor of 10, up to 200Hz, I got a resolution better than 0.001% of full scale in just a few seconds. So, it made a much better throughput with faster testing.
Later, a guy asked me for some help on a "low-frequency" PLL. I asked how low. He said 20 MHz. I explained that as far as I was concerned, 20 Hz was a low frequency. I can do PLLs much lower than 20 Hz. I can do 200 or 20 mHz, and if I was challenged, I could probably do a PLL at 20 µHz. I later made a 200-MHz PLL, controlled by a 5-MHz crystal clock. It was... challenging.
I was reminded of this when my wife asked me to take a cookie-sheet of cherries down the cellar stairs to the freezer. I told her, "And I have to be careful to not flip them all over." When I'm walking up and down the stairs in the dark, I recall that I'm walking like a PLL. I lock my speed, frequency, and phase to that of the stairs going by. I don't need to see what the stairs are doing every millisecond. I can feel where I am.
When I'm running up and down the stairs, I rely on my PLL skills to put my feet in the right places (see "What's All This Conditioning Stuff, Anyhow?" at www.electronicdesign.com, ED Online 9726). Of course, running up and down stairs is only good for your health if you don't trip, fall, and crash.
Here at National, somebody put up placards saying, "Use the handrails to walk on the stairs safely." Whenever I see that, I immediately take my hand off the handrails and continue to concentrate on walking down the stairs carefully.
When we went hiking in Nepal to the Annapurna Sanctuary in October 2005, we knew there would be a lot of stone steps. I counted them carefully. On the last two days, we descended 8820 stone steps from Ghorapaani to Birethanti. These steps are known as Gurung Staircases, and famously so. See the complete story at www.national.com/rap/nepal/annapurna.html
Over the 14 days of the trek, we ascended and descended 35,510 stone steps. In the Annapurna area, the step sizes are fairly consistent, so you don't have to worry so much about the step size. But you still have to pay some attention to where you place your feet. However, don't expect consistent step sizes in a house or hotel in Nepal. They often change wildly!
When we went on linear seminar tours about four years ago, we used to tell audiences to avoid using PLLs when they wanted a clock with low jitter. Now we tell designers to use a good PLL and engineer the loop filters carefully for a clock with low jitter.
NSC has a good Web site on PLLs at http://webench.national.com/appinfo/wireless/webench/index.cgi.It can help you engineer your loops. Some of the advice offered for 2400 MHz also may be applicable at 2400 mHz. I haven't exactly told you much about how to engineer good PLLs, but I may have pointed you in the right direction. These Web sites can be helpful.
I likeed your article very much, but can please guide me on how to design a pll with a frequency range from 500hz to 10KHz
Hassan Saleem -February 20, 2008
Could you tell me where to find the way to design a PLL with an minimum input frequency of 0.5Hz? Thank you!
Dankoro -December 20, 2007
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