Design-for-test (DFT) is essential to ensure that complex designs can be thoroughly tested. Testing demands continue to increase as designs grow in gate count and fabrication process technologies evolve. Fortunately, advances in DFT techniques have avoided major design requirements and restrictions for test. In fact, some approaches have reduced the impact of test on designs.
Structured DFT techniques are commonplace due to their high fault coverage and support by automated test-pattern generation (ATPG) tools. Scan technology and memory built-in self-test (BIST) are the foundation of most structured test techniques. A device’s sequential elements are evenly divided into scan chains that are loaded through device I/O in parallel. Multimillion-gate designs typically are forced to maximize the number of scan chains to minimize scan pattern depth and test time. This way, tester memory limitations are respected and test time requirements are met. Therefore, scan often requires many device I/O pins to load scan chains during test.
Large memories embedded within a device usually are tested with specific memory-test algorithms. The most popular memory-test approach is to use BIST circuitry to provide test stimulus and verify responses on-chip and at-speed.
However, several issues in the past few years have complicated test requirements. The population of timing-related defects has significantly increased with fabrication processes of 130 nm and smaller. As a result, at-speed scan test is now necessary to sufficiently detect these timing defects.1
At-speed scan transition tests require many more test patterns than traditional stuck-at tests. In addition, accurate clocking is needed for high-quality tests. This increases the demand on the test environment to support these additional tests. Furthermore, many companies are considering additional tests to further improve test quality, such as multiple detect patterns and deterministic bridge-targeted tests based on physically extracted layout parameters.
Test approaches can also impact the design flow. Many design teams construct the design in pieces to simplify the overall process. Designs often are partitioned into blocks that are independently designed, then assembled together at the top level. Any additional test logic or routing for test complicates this process. Unfortunately, large devices that use this type of modular or hierarchical approach often have many scan chains. Therefore, many scan routes are common at the top level.
Another test issue in many designs is the extensive use of distributed small memories. If memory BIST is used for these memories, then there could be a measurable silicon-area impact from adding multiplexing, routing, and BIST controllers. The dilemma is determining how to apply the necessary memory algorithms without causing a large impact in silicon area.
Growing test demands create several design implications that must be mitigated:
- High-speed tester clocks and fixturing for at-speed test
- High-speed I/O to support at-speed tester clocks
- Increased silicon area and routing for memory BIST of small memories
- Increased tester capacity to accommodate the application of many patterns
- Large number of I/O to support scan tests
- Many top-level routes to support scan chains
Even so, various DFT approaches can provide the desired test capabilities with minimal design impact.
Using PLLs for accurate at-speed test
An external clock is used during scan testing to load the scan chains for each pattern. Supplied by a tester, this clock usually operates at a relatively slow frequency. To apply at-speed scan tests, high-frequency clock pulses must be applied after loading the scan chains. Applying high-speed pulses from a tester can be problematic, though.
It’s difficult for a tester to mimic a device’s internal phase-locked loop (PLL) waveform. In addition, many devices have higher speed internal clocks than external I/O. So even if a tester can supply accurate clocking, special I/O pins may be required so the clocks can get from a tester to the device gates.
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