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[TechView: EDA]

A Hardware-Assisted Verification System For The Masses Arrives On Desktops



David Maliniak  |   ED Online ID #13892  |   November 6, 2006

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With an eye toward much broader deployment of hardware-assisted verification than was ever before possible, Cadence's Incisive Design Team Xtreme III series of accelerator/emulators simplifies the ability to move to and from simulation and acceleration engines. The system offers twice the performance of Cadence's earlier Xtreme Server systems, with a gain of from 10 to 100,000 times in simulation performance. Up to 72 million gates are supported.

Now that multiple languages and a complex testbench are part of the simulation landscape for many design teams, it's more critical for them to take advantage of verification technologies such as assertions and transaction-level models. The Xtreme III systems help make this happen.

Offering a simulation-like, event-driven environment, Xtreme III systems are tightly integrated with Cadence's Incisive Design Team Manager for plan-driven and metric-driven closure management. They're also integrated with the Incisive SimVision simulation-debug environment and provide support for SystemVerilog Assertions and the SystemVerilog direct programming interface. A concurrent mode lets designers run their transaction-based acceleration environment with SCE-MI 1.1, approaching maximum emulation speed.

Xtreme III is offered in two tiers. The Xtreme III Desktop entry-level system supports simulation, acceleration, and targetless emulation. The Xtreme III System also offers in-circuit emulation capabilities. Both systems accommodate up to 12 users at once. Limited quantities are available now, with full release scheduled for the end of 2006.

Contact Cadence Design Systems directly for pricing information.

Cadence Design Systems
www.cadence.com




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