FPGAs and structured ASICs are like Baby Boomers. They continue to look for ways to improve their position in life while reaping nice raises every year (in the form of revenue boosts). They're also more liberal than their elders. And, they continue to try to leave a mark on society. The main difference is that FPGAs and structured ASICs aren't looking to retire anytime soon.
On the contrary, FPGAs and structured ASICs look to expand in markets like automobile infotainment. There's also a push to move more functionality traditionally reserved for DSPs into FPGAs, such as applications that require several channels like wireless basestations.
Companies like Altera, eASIC, and Xilinx will all offer 65-nm process technology-based devices. So, it will be interesting to watch the industry this year and see how much more of a system gets implemented in FPGAs and structured ASICs.
State Of The Union According to research firm Gartner, FPGAs will grow 18% this year and maintain the highest compound annual growth rate (CAGR) over the next few years compared to ASICs and ASSPs (Fig. 1). This suggests that FPGAs will grab more market share from both sectors.
"Expect FPGAs to continue to increase market share versus ASICs as more applications adopt FPGAs and as more system functionality is implemented on FPGAs due to the high development cost of ASICs," says Danny Biran, vice president of product and corporate marketing at Altera (see "Let Innovation Resonate Throughout The Industry."
"There are two fundamental reasons why FPGAs move to the heart of the system and continue to gain market share versus ASICs," Biran says. "First, as ASIC development cost goes up, it is difficult to justify the development of an ASIC for many market segments, simply because the ROI (return on investment) isn't there. Secondly, current performance and density levels of FPGAs meet the requirements of many more high-end applications, while the price of low-cost FPGAs meets the requirements of many cost-sensitive applications."
The View At 65 nm Good evening folks, this is your captain speaking. Today's cruising altitude will be 65 nm. If you look out to the right of the industry, you can see the Xilinx Virtex-5, while off to the left we're approaching the Altera Stratix III.
Xilinx was the first to market with a 65nm offering, and its Virtex-5 devices are well known throughout the industry. They have up to 330k logic cells and 1200 I/O pins. Also, they support over 60 I/O standards and RocketIO serial transceivers, and they include a built-in PCI Express endpoint and Ethernet media-access controller (MAC).
The Virtex-5 devices, which can implement differential interfaces up to 1.25 Gbits/s, help keep signal integrity in check using digitally controlled impedance for active I/O termination. Designers may choose one of several IP controller and DSP cores, which can be integrated using power-saving features. By now, there are many product reviews, and Xilinx has a complete set of collateral available on its Web site.
The new kid in town, expected to arrive in the third quarter of this year, is Altera's 65-nm Stratix III device. It offers more control over power consumption using Programmable Power Technology (PPT). It also offers more design flexibility than past models.
PPT maximizes the performance of high-speed paths while minimizing power usage elsewhere. Each logic, DSP, and memory block is analyzed to determine if it should be placed in high-speed or lowpower mode. PPT is possible thanks to PowerPlay, a relatively new feature of the Quartus II tool that automatically analyzes the design to determine critical path signals that demand high performance. The decision to place a block in highspeed or low-power mode is based on timing constraints and the clock slack at that block.
Stratix III also can set the core operating voltage to 1.1 or 0.9 V. Designers can choose 1.1 V for applications that need higher performance and 0.9 V for applications that require minimal power consumption. Altera is the only company currently offering PPT and a settable core voltage. Furthermore, the Stratix III provides a very simple gateway to Altera's HardCopy structured ASICs, which are low-cost, functionally equivalent, and pincompatible with Stratix III.
When it comes to signal integrity, Stratix III FPGAs offer a high power- and ground-pin to userI/O-pin ratio, along with optimized signal return paths, adjustable slew rates, staggered output delays, and calibrated on-chip terminations. These features will help reduce potential issues with simultaneously switching output noise (SSO or SSN).
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