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[TechView: EDA]

Common Power Format Comes To Fruition In Tool Suite



David Maliniak  |   ED Online ID #14807  |   February 15, 2007

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As in any industry, standards in design automation can be of tremendous benefit to designers—and that's especially so in the realm of design data. The efforts to create a common format for power-related data, initially spearheaded by Cadence and other EDA, IP, and semiconductor vendors, is now under the aegis of the Silicon Integration Initiative (Si2).

The initiative's goal is to provide a mechanism through which a power architecture can be defined early in the design cycle and then carried through to implementation using a single view. The resulting Common Power Format (CPF) 1.0 specification was approved as an Si2 spec last month. Work to evolve the spec carries on through Si2's Low Power Coalition (LPC).

But standards and data formats don't get chips designed on their own merits. Tools must use the standards and formats for them to be of value. Cadence has answered the call with a complete low-power design, verification, and implementation flow that lets an engineering team, or groups of teams, leverage the CPF to capture low-power design intent at the outset of the design process and then propagate it throughout the flow.

The CPF makes it possible for the fragmented data describing the intent for a complex IC's power architecture to be read and understood by all tools. Consider the case of logic design.

Whether it's formal analysis, test-bench simulation, equivalence checking, synthesis, or place and route, all of the tools in the flow can base their understanding of logical design intent through use of a single view. (Generally speaking, that's the hardware-description-language representation.)

The CPF does the same for the power-architecture side of the design (see the figure). In the process, it also eliminates the need to cobble together a power-aware flow through tedious hand-integration work.

The Incisive Design Team and Enterprise simulators, the Incisive Design Team Manager and Enterprise Manager, the Encounter RTL Compiler global synthesis tool, and other Cadence tools have been ported to the CPFs. Together, the tools that recognize CPF comprise a flow that spans a multi-specialist project team with a common view of the design that includes the low-power intent.

Contact Cadence directly for pricing and delivery information.

Cadence
www.cadence.com




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