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[Product Innovation]
Hardware-Based IP Speeds Up Processor Multitasking
Multitasking manager eliminates task-switch overhead to boost processor performance by an order of magnitude.

Dave Bursky  |   ED Online ID #1534  |   February 18, 2002


Today's high-performance processors spend a significant portion of their processing time switching from task to task, often executing hundreds of instructions each time. In a PC, that frequently involves a multimedia task, such as viewing an MPEG file, handling a soft modem, running a word processor, accessing the disk drive, and controlling a printer. As CPU speeds go up, the processor can handle more tasks. Current PCs can simultaneously handle several major time-critical tasks and a number of less performance-critical tasks.

Embedded processors often face the same challenges and need to minimize their task-switching overheads to deal with many real-time events. Speeding up the processor is one approach to handling more tasks. But this method increases power consumption and may only allow the processor to handle one or two additional tasks.

Designers at Xyron Semiconductor have a better approach. They crafted and patented a hardware-based task manager that switches between tasks without instruction overhead. With such zero-overhead task switching, the processor can handle many more tasks without increasing the clock frequency. In fact, for some applications, a 50-MHz CPU could end up doing the work that previously required a 500-MHz processor.

For example, in a Pentium-based system that switches between three tasks, the task-switch overhead is typically about 360 cycles. When cycling through all three tasks, 1080 cycles are consumed for overhead operations. At 500 MHz, the 1080 cycles consume about 2.1 µs, and about 1.1 µs at 1 GHz. Although that time may seem small, that overhead can get in the way of real-time operations, such as multimedia playback, or high-speed data communications if the overhead is a large percentage of system execution time.

Xyron's technology is called ZOTS, short for zero-overhead task switching. It greatly reduces or eliminates the interrupt latency and task-change processing overhead delays in processor architectures. ZOTS greatly accelerates processor performance by enabling the system to completely save the task state, or restore the task state between cycles, without software intervention. It's available from Xyron in two forms.

The first form, a 32-bit proprietary architecture processor, executes a MIPS-like instruction set and has the ZOTS acceleration technology embedded within it. Also known as the Xyronium processor, it will come in the form of a synthesizable core configurable in a Virtex II FPGA from Xilinx Inc. To support application development using the Xyronium core, Xyron also offers a development board optimized to handle such applications as video manipulation and storage, real-time industrial control, and networking.

The second form of ZOTS technology is pure intellectual property (IP). Xyron expects to license the IP to companies that design CPUs, DSP engines, and other compute engines for internal ASIC consumption and resale.

Adding ZOTS to a processor requires the design team to add read and write ports to the register files and make small changes throughout the processor, so that it would become more task aware. The task manager and the task storage from Xyron are essentially unchanged from processor to processor, so minimal, if any, changes would be made to the ZOTS technology.

By placing the task management into the silicon and storing all task information in a local static RAM, Xyron's designers crafted a system that could manage hundreds of tasks. The ZOTS approach includes the ability to handle variable-priority ramping, enabling priorities to change and be re-evaluated every cycle (Fig. 1). It permits deadline scheduling for high-priority tasks, plus pre-emptive and round-robin scheduling.


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