Accellera has given the nod to version 2.0 of the Open Verification Library (OVL) as an Accellera verification standard. The OVL supports assertion-based verification (ABV) with Verilog, SystemVerilog, VHDL, and the Property Specification Language (PSL).
The standard includes an open-source library of assertion checkers that allow reuse in various verification environments. The OVL itself is a vendor-neutral and language-independent assertion methodology to functionally verify designs in simulation and formal verification environments.
New in version 2.0 of the OVL is the ability to synthesize assertions into emulators, accelerators, and FPGA prototyping environments. This extends assertion-based verification with OVL to support the full verification flow, with simulation, formal verification, hardware-assisted verification, and FPGA prototyping.
Version 2.0 also adds synthesizable checkers that include "enable" and "fire" ports for additional control of the checkers when used in hardware flows including emulation, FPGA prototyping, or ASIC error detection. There are also 17 new and more advanced checkers, taking OVL to a total of 50 assertion checkers that cover many of the common properties that engineers check during functional verification.
Additionally, there is now a VHDL implementation of the 10 most popular checkers, as well as finer control of X checking on a per-instance basis. Version 2.0 is backward-compatible with previous versions of Accellera OVL.
The Accellera standard OVL 2.0 is available now for download at the Accellera Web site. Additional information and examples are available at the OVL Users Site: www.edastds.org/ovl.
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