Power consumption is a primary design consideration for today's systems-on-a-chip (SoCs). Consequently, pervasive powerreduction techniques are now an established part of the design process from register-transfer level (RTL) to final layout.
Static timing analysis (STA) is squarely in the critical path for getting to silicon. Design for power adds yet another set of requirements to this process. In the same way that a critical timing violation can drive the need for additional engineering change orders (ECOs), failure to meet a power budget can cause a major disruption in the design closure process.
Many of the design techniques used to reduce static and dynamic power directly influence timing and the application of STA. For example, selecting high-VTH cells to reduce leakage will increase path delay. Likewise, inserting level shifters between multiple voltage domains will delay signals crossing power domains.
Clock gating decreases dynamic power by reducing switching activity, but impacts clocktree insertion delay and clock skew. STA must take these, and other low-power design techniques, into account to provide accurate analysis and ensure the resulting device works to specification.
Power-optimization techniques are not complementary to achieving timing closure, and the relationship between power, timing, and area is not always intuitive. Attempts to reduce power at the gate level can negatively affect timing and area, sometimes requiring a redesign of the RTL code. RTL changes, late in the design cycle, result in additional iterations through synthesis. They also complicate STA and delay signoff.
However, there is greater opportunity to reduce power earlier in the design process, with less impact to design closure. By optimizing power prior to RTL synthesis using automated techniques that consider timing and area, designers can reduce one hurdle in design closure; decrease iterations through RTL, synthesis, and STA; and meet timing faster (see the figure).
Of course, STA tools must still accommodate and account for power-reduction techniques. Additional ECOs for power optimization can be reduced as well.
With today's designs, it is not a matter of if you'll need to optimize for power. It is just a question of when you do it. Designers should optimize power early in the design process to avoid adding yet another degree of uncertainty in the STA process and delaying signoff.
Mitch Dale is director of product marketing for Calypto Design Systems, Santa Clara, Calif. He holds a BS in applied mathematics and computer science from UC Berkeley. He can be reached at mdale@calypto.com.
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