Today's increasing processor speeds and bus and networking data rates have made electromagnetic interference (EMI) a major headache. EMI compromises a design and interferes with nearby circuits. It also forces special hardware measures to meet FCC and other regulations. Yet SpectraLinear's fully programmable SL15100 and SL15101 spread-spectrum clock generators (SSCGs) can drop EMI to a practical level.
Spread-spectrum clocking is finding its way into more products. EMI is mostly generated by the very high-speed clocking signals that drive the processors and other chips, including switching power supplies. Fast rise and fall times produce a huge number of odd and even harmonics at very high levels. The clock signal and some harmonics have peak energy levels that exceed FCC Class A and Class B Part 15 EMI limits (Fig. 1).
Common techniques like filtering and adding shielding can solve the problem but also lead to higher costs and larger and more costly hardware. By factoring spread-spectrum clocking into your design at an early stage, such EMI mitigation measures may not be necessary.
Spread-spectrum clocking is a technique for frequency-modulating the clock over a very narrow range. It adds a controlled jitter by linearly increasing and/or decreasing the clock frequency slightly. This modulation spreads the signal energy over a much wider bandwidth. Since the total energy in the signal is the same as the single frequency clock but the bandwidth is wider, the spectral components occur at a much lower level. With this technique, you can often reduce the EMI to desired levels.
Also, spread-spectrum clocking is implemented with a phase-locked loop (PLL). The external clock signal either from a master crystal oscillator or some other clock source is applied to the PLL, and the voltage-controlled oscillator (VCO) tracks the signal. By modulating the VCO internally with linear ramps, the output signal can be "dithered" or varied in frequency slightly. The PLL also provides clock frequency multiplication to achieve some higher data rate. Adding frequency dividers provides greater flexibility in generating the various clocks required by the system as well.
The SL15100 and SL15101 can be used in practically any consumer or commercial product. They're based on a PLL clock multiplier with built-in frequency dividers and switch circuits (Fig. 2). The SL15100 produces two outputs, while the SL15101 has four outputs.
The output frequency ranges from 3 to 200 MHz. The input can come from a crystal oscillator or any other clock source. The frequency modulation changes the output frequency over a programmable 0.25% to 5% range. It can be set up to produce either centeror down-spread modulation. The spread modulation frequency can vary from 30 to 120 kHz of the center frequency.
The clock input is sent to a gain stage before being applied to the PLL. The inputs also have built-in variable crystal load capacitors (8.5 to 40 pF in steps) that allow designers to tune the external crystal to the chip. The four outputs can be independently programmed for the same or different frequencies.
The chips provide seven levels of programmable rise/fall times on the output for impedance matching to fine-tune the clock to the application. Depending on the supply voltage, rise/fall times from 0.55 to 4.8 ns can be selected in seven steps. The spread-spectrum clocking can be switched off on any of the outputs. Programming is via two of the multifunction output pins.
Available now, these SSCGs come in an eight-pin thin-shrink small-outline package (TSSOP) and operate from 2.5 to 3.3 V dc. Pricing is $1.58 for the SL15100 and $1.73 for the SL15101, both in 1000-unit lots.
SpectraLinear Inc. www.spectralinear.com
Reprints
