Now that an electronic system-level (ESL) tool vendor is using the term “ESL 2.0,” I can hear the snickering already, especially from the hardcore RTL camp. Is this just some kind of marketing ploy intended to sell more of the same-old? Or is there more than meets the eye?
Marketing ploy or not, ESL is to some extent a state of mind. As one of the earlier entrants in the ESL arena, CoWare has been rethinking its approach, especially in light of today’s system-on-a-chip (SoC) design challenges: network-on-chip architectures, multicore designs, and multiple, dependent software stacks. CoWare’s stance is that with these challenges, the industry has reached an inflection point in ESL adoption.
What’s new about CoWare’s latest release is its comprehensive approach to the building of virtual platforms (see the figure). The release spans six areas: platform architecture design, software development, platform verification, application subsystem design, processor design, and DSP algorithm design.
Thanks to the introduction of design starter kits that can be used as templates, users in production environments gain a 50% improvement in ramp-up time. Further, a number of additions to the release bring a tenfold productivity improvement to the modeling of multicore platforms.
A SystemC Component Wizard provides for automatic testbench creation, while a Bus Library Wizard quickly performs interconnect setup. An expanded IP model library includes new processor, interconnect, and peripheral IP models as well as a new wireless library for DSP algorithm design. Platform simulation is up to 200% faster, while instruction-set simulation is up to 400% faster.
CoWare’s ESL 2.0 solution is available now. Pricing varies based on the tool configuration.
CoWare
www.coware.com
Reprints
