True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the resulting timing-verified, gate-level netlist is handed to the ASIC vendor, who takes over with more floorplanning, detailed place and route, and output of GDSII for fabrication. As a rule, register transfer level (RTL) designers don't care about implementation, and place-and-route experts don't give much thought to what's in the RTL.
If you answered "true" to all, or even most, of the above, you may, at best, be designing very simple and relatively slow ASICs in 0.35-µm process technology. At worst, you could be sitting on a more ambitious ASIC design that will never see the light of day. If, however, something didn't ring quite right, it's probably because you've woken up to the reality of ASIC design in the third millennium.
That reality is this: At 130-nm and smaller process ge-ometries, the days of the nice, clean handoff of a gate-level netlist to an ASIC vendor are very much over. Even if ASIC design meth-odologies never vary from the tried-and-true formula of gate-level netlist handoff, something has to give.
ASIC vendors are finding that the gate-level netlist, based as it typically is on statistical wire-load models, doesn't convey nearly enough information for accurate delay calculations. In this day of interconnect delays that easily swamp gate delays in terms of their overall contribution to timing, the traditional gate-level netlist is a recipe for disaster. More often than not, the result is an endless cycle of iteration from synthesis to floorplanning and global placement and routing, back to synthesis, in an effort to achieve timing goals (Fig. 1).
According to Dave Reed, vice president of solution delivery at Monterey Design Systems, "Starting at 0.35 µm, and certainly by 0.18 µm, you had to look not just at a statistical wire-load model, but also at the physical placement, to get an idea of what the wire length was going to be, so you could accurately model the delay. The problem is, for sure with 0.13 µm already and, no doubt, 90 nm, just knowing the placement isn't nearly enough to have all you need to know to close the design. You need to get information from the routing world too."
It appears that at least one of two things must happen in the ASIC flow as process geometries drop to 130 nm and smaller. RTL designers must develop an awareness of, and a methodology for ascertaining, the effects on implementation of their RTL code. Some tout such techniques as the only way out of the iteration quagmire that plagues traditional methodologies. Tools that analyze RTL to look ahead to its impact on physical implementation are beginning to make their presence felt. Others that build virtual prototypes from RTL to examine how delays will shake out promise to break the synthesis/place-and-route iteration deadlock.
Less certain, but still worth examining, is the need for a shift in the point at which ASIC designs are handed off for implementation. Some would have ASIC design teams pass their designs over for implementation at a higher level of abstraction than a synthesized, gate-level netlist. Proponents of RTL handoff point to the advantages of not separating synthesis from place and route as is done in the traditional front/back-end split.
Others would take the handoff point to a place farther down the road to implementation, suggesting that the synthesized netlist should be brought down to the level of placed gates. Placement-based handoff, as this is sometimes called, would by necessity include a global route. Going in this direction would, at least, give the designers more to go on in terms of physical information and, it's thought, a better shot at timing closure.
Finally, others say that the customer-owned tooling (COT) model makes the most sense as an ASIC methodology. In a COT flow, the typical scenario is for a system house to directly work with a pure-play foundry. A COT flow generally means that the system house takes its design all the way through to physical implementation. The resulting GDSII representation of the design is, in theory, ready for fabrication and packaging.
To some extent, the handoff point is a business-model decision. It also is a matter of risk and who assumes it. System design houses with the expertise to take the COT route are relatively few. If you're an ASIC vendor, that's good news. COT flows and ASIC vendors generally don't mix, as ASIC vendors lose much of their opportunity to provide value-added services in such scenarios. Taken as a group, EDA tool vendors, ever-hopeful of coming up with an answer to the deepening design gap, seem to be pointing in conflicting directions.
The question of what must happen at the RTL stage of the ASIC design process is much clearer. More physical information must be accounted for in the front end of the cycle. "Pushing physical information forward is clearly happening," says George Janac, president and CEO of InTime Software. "Wire-load models don't mean a thing. I think there's going to be more tools that let RTL designers look downstream and determine what timing will really look like."
There are three primary ways to move physical information forward into the front-end flow: virtual prototyping, floorplanning, and RTL analysis. The idea of virtual prototyping is to give the front-end designer a set of tools that rapidly maps a design into a rough estimate of what the physical design might look like.
But, says Bob Smith, vice president of marketing at Magma Design Automation, it's important to provide the front-end designer with that physical insight in a way that gives him data that he's used to seeing, rather than forcing a move into full-blown physical design. "When they get to the next handoff point, they have a good degree of comfort that the chip can be laid out and routed," says Smith.
"Designers are finding that they have to go farther and farther into the physical domain, and bring those ramifications into the design cycle," echoes Suk Lee, vice president of marketing for ASIC programs at Cadence Design Systems. But at the same time, Lee maintains, they're trying to avoid becoming silicon experts. "Otherwise, why not just go COT?"
For its part, Cadence is working toward what it terms a virtual physical prototype-based handoff. Such a strategy entails a placement-based handoff that's augmented with detailed information about the actual nanometer wires that connect gates. "In a traditional front- and back-end methodology, the first time you see those wires is in the detailed routing stage," says Lee.
Among early entrants in the virtual physical-prototyping arena is Cadence's Encounter RTL-to-GDSII architecture for nanometer-scale digital design implementation. The system accounts for such factors as IR drop; delays, which are based on layer assignment and coupling capacitance; and any crosstalk effects. Through a trial-detailed route, the tools provide a detailed representation of the wires at every stage of design implementation.
Agere Systems has signed on with Cadence for purposes of providing its ASIC customers with a temporary First Encounter license. Agere's goal is to enable customers to deliver designs that are more likely to meet first-silicon success. As a result, Agere itself can shorten the back-end implementation cycle through elimination of the typical iterations across the front- and back-end divide.
Hybrid techniques are available that combine floorplanning, virtual prototyping, and RTL analysis as well. One example of this can be seen in Tera Systems' TeraForm RTL Design Planner. Tera's approach centers on the notion that to succeed in nanometer ASIC design, RTL designers must know more about physical design. Likewise, place-and-route experts ought to know more about what's going on in RTL. But neither should have to become experts in the other's domain.
"The 'gotcha' in the middle of this is a knowledge gap," says Mark Miller, Tera's vice president of marketing and business development. According to Miller, the design teams are asked to assimilate new technology and skills in the placement realm. Conversely, the ASIC vendor's support organization is filled with layout and place-and-route experts. Their aptitude in language-based design isn't that high, nor do they know much about synthesis. In the end, Miller contends, the knowledge gap is that both sides of the equation need each other's knowledge to successfully move the handoff point in either or any direction.
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