Electronic Design

  
Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


[Embedded in Electronic Design]
Development Tools

William Wong  |   ED Online ID #1773  |   December 9, 2002


Flash DSP/MCU Ropes In C/C++
Merge a 32-bit DSP and a 16-bit microcontroller (MCU) into a single integrated unit and you've got one of Motorola's latest developments, the 56F800 architecture. Fast interrupt support allows the chip to handle signal-processing tasks with features like single-cycle instructions, and no overhead hardware looping functions can take advantage of bit manipulation and other capabilities. A memory-based stack and large register file suits it as a C or C++ target platform.

One version of this chip, the new 60-MIPS 56F83x, runs at 60 MHz with a standard operating temperature range of -40°C to 125°C. Peripherals include analog-to-digital converter (ADC) and pulse-width modules, quad timers, quadrature decoders, and a 2.0B FlexCAN module. Flash memory size ranges from 12 to 256 kbytes. A security feature prevents code access and corruption. Additionally, a 256-word page size allows EEPROM emulation.

Pricing for the 56F800 will start at $5.22 in OEM quantities. www.motorola.com

16-Bit DSP Architecture Boosts MCU
Set up for C, Microchip's 30-MIPS dsPIC30F family homes in on the 16-bit DSP space with a microcontroller's peripheral complement. The 16-register-bank architecture is a major advance over the company's 8-bit PIC microcontrollers (MCUs), but the dsPIC30F retains MCU features like a programmable brown-out reset and a low-voltage detect interrupt.

The data converter interface supports common codec protocols such as I2S and AC'97. A 10-bit analog-to-digital converter (ADC) handles up to 16 channels with two or four simultaneous samples. Communication support includes addressable UARTs for controller-area networks (CANs). Moreover, an I2C module features multimaster mode and 7- and 10-bit addressing.

When it comes to memory, the dsPIC30F is flexible. A three-address generation unit handles dual data fetch and writeback for DSP operations. Up to 4 kbytes of EEPROM, 8 kbytes of SRAM, and 144 kbytes of flash memory are included. The address space for programs is 4 Mwords and data is 64 kbytes. www.microchip.com


Reprints   Printer-Friendly  Email this Article  RSS    Font Size   What's This?


  • C Tools Accelerate HDV Development On Xilinx FPGAs
  • A New Design Inflection Point
  • Forecasting Industry Growth For 2009 And Beyond
  • EDA Retools To Exploit Multicore Architectures
  • Design And Verification Move Up In Abstraction
  • EDA Retools To Exploit Multicore Architectures
  • A New Design Inflection Point
  • Design And Verification Move Up In Abstraction
    1) Transportation Guidelines For Lithium Batteries Get Updated
    (1224 views today)
    2) Build A Smart Battery Charger Using A Single-Transistor Circuit
    (282 views today)
    3) WHITE PAPER: Liquid-Level Monitoring Using a Pressure Sensor
    (204 views today)
    4) 1-A Switching Regulators Operate With 96% Efficiency To Replace Linear Regulators
    (137 views today)
    5) The Field Of Energy Harvesting Begins To Ripen
    (107 views today)
    ALL TOP 20



    Reader Comments

    Either I am not looking at the article on development tools or this is the cheapest promo I have ever looked at. sigh...

    Embedded Engineer -December 14, 2007

    POST YOUR COMMENTS HERE
    Name:

    Email:
    Your Comments:

    Enter the text from the image below


    Please refresh the page if you have trouble reading this text.

    Search Electronic Design
         
      
     
    Web Seminar
    Sponsored By:
    Title: Read Pacing: A Performance Enhancing Feature of PCI Express Gen 2 Switch Devices
    Speakers: 
    Date: 07/01/08
    Register: 

    Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF
    Mobile Dev & Design Schematics Find Power Products Military Electronics EE Events Related Resources