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EDA Alert e-Newsletter | December 4, 2007
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Visit Synopsys TCAD At 2007 IEDM December 10-11, 11 am to 8 pm The Churchill Hotel, Washington, D.C.
Learn about the Sentaurus TCAD simulation tools that address a variety of applications including strained silicon CMOS, multi-gate FETs, SiGe HBT, memory, image sensors, silicon and wideband-gap power devices, and III-V compound devices.
Designers Must Yield To Change By Robert Hum, VP and General Manager, Design Verification and Test Division Mentor Graphics Corp., San Jose, Calif.
Two changes will occur in manufacturing test products in response to market pressures: embedded compression tools and logic built-in self test (LBIST) will converge; and manufacturing test tools will be integrated with yield and failure-analysis tools and looped back into design tools to improve yield for ICs at 65 nm and below.
eASIC And Tensilica In Deal To Lower Cost Of Embedded SoC Development
A partnership between Tensilica Inc. and eASIC Corp. aims to lower the costs of developing custom embedded SoCs by enabling eASIC to provide free access to Tensilica's Diamond Standard microprocessor and DSP cores for its free mask charge, no-minimum-order ASICs. Through this partnership, embedded system designers can now develop Diamond processor-based SoCs for applications in any production volume.
FPGA Design Flow Takes Simulink Code Into Synthesis
Thanks to collaboration between The MathWorks and Mentor Graphics, MathWorks' Simulink HDL Coder users gain a smooth path into synthesis. Mentor's Precision Synthesis tool now supports HDL generated by Simulink HDL Coder, enabling users to directly create optimized netlists for FPGAs.
Tool Designs Passive Components For RF Applications
Designers of high-speed and complex wireless SoCs and RFICs need a means of creating passive components. Cadence's Virtuoso Passive Component Designer represents a complete flow for the design, analysis, and modeling of inductors, transformers and transmission lines.
Design-to-Mask Software Beats Mask-Prep Data Crunch
Shrinking process geometries and circuit complexity have conspired to create an explosion in data volumes for advanced IC manufacturing. Dealing with the oceans of data can result in longer development times. Most deeply affected are the mask-synthesis steps (RET and OPC) and mask-data preparation (MDP).
In the Dec. 13 issue's Engineering Feature, Technology Editor Mat Dirjish will look at what's next in digital home technology. What would you like to see most in your home of the (near) future?
Portable Designs with High-Power Batteries and Chargers Wednesday, December 5 at 2:00 pm ET; presented by Micro Power
Robin Sarah Tichy, PhD, Technical Marketing Manager at Micro Power Electronics Inc. provides an industry update and profiles new high-power (or high-pulse) rechargeable lithium batteries. Traditional lithium batteries support pulses of 5 A, while new high-power batteries support pulses over 100 A, enabling many new portable applications. This Webcast details cell configurations, chemical formulations, electrical performance, safety issues, limitations, and sample performance data.
Send us your Ideas for Design and we'll pay you $150 for every Idea for Design that we publish. In addition, the year's top design as selected by our readers will earn an additional $500, with two runners-up each receiving $250. You can submit your Ideas for Design via e-mail to: dbs@penton.com or, mail your material to:
Ideas for Design Electronic Design 45 Eisenhower Dr., Suite 550 Paramus, NJ 07652
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