Dennis Monticelli, National Semiconductor’s chief technology officer, is happy to speculate about the coming year. Like other analog semi companies, National will continue to reduce power requirements, he said, adding that the company will introduce high-definition, broadcast video components that handle four times the bandwidth of standard-definition components at the same power. National also will offer new-generation cable equalizers that require no power at all.
“As the deployment of video-enabled portable devices continues to grow, we will see a dramatic increase in the infrastructure required to support them,” he said. “As a result, higher-efficiency switching regulators will emerge along with novel technologies for reducing power-supply size without compromising performance.”
Improving the Old
Analog Devices provided a different perspective, homing in on the redesign of one group of products to illustrate the idea that no design is ever really finished. The objective was to make the company’s direct digital synthesis (DDS) chips more attractive than phaselocked loop (PLL) or FPGA alternatives in wireless and portable devices.
ADI aims to do so by reducing power consumption while maintaining the DDS ICs’ intrinsic advantages. These include faster settling time and higher resolution than PLLs, as well as better spurious-free dynamic range and a smaller footprint than FPGAs with embedded DDS functions driving external DACs.
The power reduction was substantial. The first improved DDS, the AD9913, can operate with a 250-MHz clock while consuming as little as 50 mW. Yet ADI’s Jeff Keip says the power reduction is the sum of a number of incremental improvements. What’s intriguing about the new part is the effort that went into cleverly resolving a situation that few would have considered an issue.
Architecturally, the AD9913 resembles the earlier ADI DDS chips, down to its 32-bit tuning word (Fig. 1). What’s different is the way it lets users precisely hit certain frequencies. Sometimes, 25.000000023283064365386962890625 MHz isn’t precise enough when you start with a 250-MHz clock and want to generate a sinewave of precisely 25 MHz.
To understand what the engineers did, look at that accumulator block at the top of the diagram. Apart from the tinted block, that’s exactly what’s used in all of ADI’s DDS ICs. On the surface, the synthesis process seems simple.
The output of the DDS, FO, is related to the clock frequency, FS, by FO = X/2C × FS. X is the frequency-tuning word, and C is the number of bits in the accumulator.
The accumulator recursively sums the digital input tuning word at the rate of the sample clock. This produces a time-series of digital words at the output of the accumulator that increases linearly until the accumulator rolls over at its maximum value of 2C.
Its output is truncated and fed into the angle-to-amplitude converter, which maps those words to one revolution on the unit circle. The output of the converter feeds an on-chip digital-to-analog converter (DAC). The average rollover rate of the accumulator determines the DAC output frequency.
In an ADI applications note, Ken Gentile provides a rigorous mathematical analysis that demonstrates that this approach cannot generate certain useful frequencies (FS/10, for example) because the accumulator modulus is fixed and the tuning word must be an integer.
The clever thing the ADI designers did in the new generation was to make the modulus adjustable. The app note also details how that makes it possible to synthesize the otherwise unavailable frequencies.
Making the accumulator modulus programmable requires a secondary accumulator (the tinted block in the figure). Figure 2 shows more details of the difference between the accumulators in previous DDS chips and the AD9913.
Fostering Collegiality
I first got interested in how companies managed engineers in remote design centers (RDCs) when I talked to Kevin Leary at Analog Devices in 2006 (see “Better, Faster, Cheaper” at www.electronicdesign.com, ED Online 14997). My interest was reawakened last fall, when Intersil invited me to a dinner that was the capstone event to a three-day internal consortium for all of its designers from all of its worldwide design centers.
For this issue, I sent out a questionnaire to multiple companies, asking how they created RDCs and how they managed the design process across all those borders.
First, I talked to Gerald “Woody” Smith at Analog Design Consortium (ADC) in San Jose, Calif., which is an ad-hoc organization of some of the best West Coast analog/mixed-signal chip designers. “A project may have RF blocks from Bulgaria, PLLs from Silicon Valley, and other analog blocks and digital blocks from Los Angeles, while using layout and fabrication resources in Taiwan,” Smith said.
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