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EDA Alert e-Newsletter | December 18, 2007
Electronic Design Announcement
Your Ideas For Design Can Win $500
Send us your Ideas for Design and we'll pay you $150 for every Idea for Design that we publish. In addition, the year's top design as selected by our readers will earn an additional $500, with two runners-up each receiving $250. You can submit your Ideas for Design via e-mail to: dbs@penton.com or, mail your material to:
Ideas for Design Electronic Design 45 Eisenhower Dr., Suite 550 Paramus, NJ 07652
TLMs Bring Benefits To Design And Verification By Wally Rhines, Chairman and CEO Mentor Graphics Corp., Wilsonville, Ore.
Design complexity has reached a point where RTL is no longer a viable starting point for verifying most silicon systems. RTL design optimization and simulation has become so time-consuming that they now threaten product schedules. However, new methodologies like transaction-level modeling (TLM) are emerging to support faster verification and design feedback.
One reason why electronic-system-level (ESL) methodologies haven't been adopted more rapidly is the massive timesink of model creation and verification for the development of virtual prototypes. JEDA Technologies is seeking to rectify that problem through its NSCvCC, a code-coverage tool for C/C++ and SystemC designs.
With chip complexity on the rise, RFIC designers need to simulate as much of their creations as possible. The alternative is greater risk of respins. Intended to speed the design of large-scale RFICs for wireless communications products, Agilent Technologies' GoldenGate Plus performs RFIC simulation, analysis, and verification.
It'd be difficult for any Web site purporting to offer "comprehensive chip-planning capabilities" to overlook the vast array of IP offered by Synopsys in its DesignWare portfolio. So to remedy such a situation, Chip Estimate Corp. has enlisted Synopsys in its Prime IP Partner Program.
Collaboration Pairs PCB Design Tools With CAD/CAE Tools
A collaboration between Ansys Inc. and Zuken Inc. will team the latter's electronics computer-aided design (ECAD) tools with the former's Workbench simulation environment. As a result of the collaboration, the Ansys Workbench platform now provides thermal, mechanical, and electromagnetic simulation capabilities to the complex component/board/system geometry in two Zuken software environments: CR-5000 and Board Modeler.
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