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EDA Alert e-Newsletter | January 8, 2008
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Webcast: "Leveraging ESL Techniques for Low-Power Design" Wednesday, February 13 @ 11 am PT/2 pm ET Presented by Mentor Graphics
Power optimization has become one of the primary goals of SoC designers in this age of portable/wireless systems. This webcast will examine what is to be gained for low-power SoC design at levels of abstraction above RTL. It will also look at how tools and methodologies are evolving to suit power optimization. You’ll learn about new ESL modeling methodologies and IP reuse concepts with which designers can efficiently build TLM SoC platforms that can accommodate accurate power assessments and substantial power optimization under real-time use cases.
In an effort to further improve the Open Core Protocol's (OCP's) ability to speed IP integration, the OCP International Partnership has opened its new debug specification to member review. The specification details an approach to a standardized OCP bus-compliant debug interface.
In Version 5 of the DesignWorks Professional schematic capture package for Windows-based computers, users will find new schematic-drawing features like graphic drawing tools and direct PDF export. Further, a powerful scripting capability has been added for advanced users and OEMs that wish to customize the package for a variety of diagramming applications.
IC and custom-ASIC manufacturer iC-Haus GmbH has switched to Synopsys' HSIM-XA mixed-signal simulator to simulate their zero-defect mixed-signal chips.
VHDL 2008: Just The New Stuff By Peter J. Ashenden and Jim Lewis
I can hear some of you asking the question already: "VHDL" That's still around?" For those coming to VHDL for the first time, it might not be the best starting place. But for those users who are already familiar with the language, this is an ideal source for "the new stuff" in VHDL-2008.
Low Power Methodology Manual: For System-On-Chip Design By Michael Keating; et al.
Undertaking the design of a system-on-a-chip (SoC) is complex enough on its own merits. As is ever more the case, when power consumption is the primary design constraint, it becomes a task of enormous difficulty. This book is thoroughly recommended to anyone embarking on a low-power SoC project.
Send us your Ideas for Design and we'll pay you $150 for every Idea for Design that we publish. In addition, the year's top design as selected by our readers will earn an additional $500, with two runners-up each receiving $250. You can submit your Ideas for Design via e-mail to: dbs@penton.com or, mail your material to:
Ideas for Design Electronic Design 45 Eisenhower Dr., Suite 550 Paramus, NJ 07652
In our January 31 cover story, Contributing Editor Ron Schneiderman will look at the role of power efficiency in today's designs. How important is power efficiency in your current projects?
Reduced power consumption is our number-one goal.
Power efficiency is one of our key goals.
We trim power where we can, but not at the expense of other specifications.
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