Few things are more frustrating than a requirement for some feature that exceeds the ability of your present hardware. Say you’re designing a product that has historically required an 8-bit digital-to-analog converter (DAC). Conveniently integrated on the system microcontroller, the DAC has never been a problem until marketing suddenly insists that it is absolutely necessary for the DAC to output 10 bits.
Of course, it’s too late to change microcontrollers, and the budget won’t support using an external DAC. Fortunately, 10-bit performance can be achieved with an 8-bit DAC by dithering the DAC between two values and filtering the output to remove any ripple.
DACs generate a particular ratio of their reference. Resolution (Δ or LSB) is the range (the total possible span of the output) divided by the total number of possible steps. For example, an 8-bit DAC with a 5-V reference has a range of 5 V across 256 (28) possible steps with a resolution of 19.53 mV (5 V/256). If this particular DAC is set to 63, its output will be 1.23 V (5 V * 63/256).
To increase resolution, it’s necessary to generate multiple values for each step. Achieving 10-bit performance with an 8-bit DAC requires 2(10-8) or four values for each step (see the table). The value to be outputted is stored as two bytes, n and the dither value (Fig. 1). The dithered value determines how often the DAC value is increased by one. The actual DAC output value can be computed in an interrupt routine, running at an appropriate update rate, using the following algorithm:
DITHERS AND RIPPLES Suppose that the dither value is set to 0x80. Adding the dither value to the accumulator results in a carry every other step. It also causes the value sent to the DAC to be bumped up a count every other step. Likewise, setting the dither value to 0x40 causes the carry to be generated every fourth step, and setting the dither value to 0xC0 causes a carry to be generated three out of four steps. Repeatedly dithering the DAC value in this way generates the desired quarter steps in the DAC output.
Unfortunately, dithering introduces a peak-to-peak ripple of Δ, which will need to be filtered to average out the signal. For a 10-bit system (Δ10bit) using an 8-bit DAC (Δ8bit), I have found an acceptable amount of ripple to be ±0.25Δ10bit or ±0.0625Δ. A specific application with a tighter ripple requirement would require more filtering. Conversely, a looser ripple requirement would require less filtering.
Suppose you want to generate a DAC output of n + 0.25 at a rate of 100 kHz. The output will be the higher value (n + 1) one time followed by three normal values (n). This generates a pulse with a 25% duty cycle and frequency of one-quarter the update rate or 25 kHz. The resulting ripple is +0.75Δ and –0.24Δ.
The ripple can be reduced to an acceptable level by filtering the output with a two-pole low-pass filter with a cutoff frequency that is one-twelfth of the update rate. If less ripple is desired, the filter’s bandwidth can be reduced. If more ripple can be tolerated, the bandwidth can be increased. Setting the bandwidth to one-twelfth the update rate for an acceptable amount of ripple is a good rule of thumb (Fig. 2).
Generating a half step results in a first harmonic greater in amplitude than for a quarter step. One might suppose this should make the signal harder to filter. But fortunately, the output frequency has doubled to half the update rate or 50 kHz. The same filter easily removes enough of the ripple (Fig. 3). Known as deltasigma modulation, this type of dithering is guaranteed to make the frequency of the dithered output be as high as possible.
Take an 8-kHz low-pass filter, for example, set below the required 8.3 kHz to allow for component tolerance (Fig. 4). It should be built with 1% resistors and 5% ceramic NPO capacitors. While the op amp should have a gain bandwidth of at least 10 MHz, it can be as low as 1 MHz and still produce acceptable results. This filter can be easily scaled to your particular application. If your update rate is only 10 ksamples/s, just increase the resistor values by a factor of 10.
I have used this technique in the past when hardware was done and I was stuck with too few bits. Actually we ended up turning a 12-bit DAC into a 14-bit DAC. Since the output was nearly DC and the DAC was inside a control loop, 1) a simple R/C removed the dither and 2) the linearity was corrected by the loop. Sometimes a practical technique such as this can be quite valuable in a pinch!
Kelly Clifford -March 14, 2008
Dear Mr. Scott,
Thank you, you make a good point about linearity of DACs. A real 10-bit DAC will have roughly four times better INL and DNL than that of an 8-bit DAC. The 8-bit DAC enchanced to 10-bits also suffers the same linearity problems. However, if an 8-bit DAC is montonic, then so is the enhanced 10-bit version.
The real propose of this column was to show the working engineer, in a pinch, how to get by with what hardware is avaliable. I also wanted to introduce the concept of dithering for future columns. I didn't mean to suggest that someone should try to substitute an 8-bit DAC for a 10-bit just to save a couple cents. Your letter makes it clear that I should have been more emphatic on that point -- thanks again.
Best regards,
Dave Van Ess
Dave Van Ess -March 06, 2008
I must take issue with the assertion by Dave Van Ess in his article "Squeeze 10-Bit Performance From An 8-Bit DAC" in the Feb. 28th issue of Electronic Design. Nowhere in his article does he mention that real 8-bit DACs do not have perfectly spaced steps in their transfer function. Real DACs barely have monotonicity - that is the quality that each higher digital code results in a higher analog output. Real 10-bit DACs normally have linearity specs that are four times better than those of 8-bit DACs. All his dither method does is divide each analog step in the ramp function into four smaller steps. But if the basic DAC just barely meets the monotonicity specification, then there could be some analog steps that are almost non-existent. That is, the analog value for code 'n+1' is nearly the same as the analog value for code 'n'. When that essentially null step is divided into four steps by dithering, then the result is four steps that all have nearly the same analog value. This would certainly not meet the linearity specifications of a true 10-bit DAC. In fact, it would have no better linearity than the basic 8-bit DAC. About the only real benefit that can be guaranteed by dithering is that the size of the largest step is indeed reduced by a factor of four. But it the linearity does not improve at all.
Robert Scott Real-Time Specialties
Robert Scott -March 06, 2008
From an editing point of view, ? has been corrected throughout.
Editor -March 06, 2008
Interesting approach, and probably useful in some contexts, but there are a few problems with it.
There is no mention of the accuracy or linearity of the 8-bit DAC. If the accuracy of the MSB (or two MSBs) of the DAC is just barely good enough to qualify the part as an 8 bit DAC, then using this article's technique will result in a 10-bit DAC that is not monatonic -- that is, when the value crosses the middle of its range (and perhaps even 1/4 and 3/4 of the range), the output voltage can actually go down when the digital input value goes up, and vice versa. In many applications, this can eliminate the advantage that was hoped for in a 10-bit device. It is possible to account for this using techniques similar to those described in the article, but the solution probably requires a lookup table and a lot of testing for each part. If there was not enough money to move to an external 10-bit ADC, there is almost certainly not enough money to test each 8-bit ADC, generate a lookup table, and program the table in each system.
From an editing point of view, there are several ? characters in the version of this article that is on the web that makes it less useful, or at least harder to understand.
Anonymous -February 28, 2008
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