Elegant designs have always blended old and new while meeting certain criteria. In the case of VIA Technology’s Isaiah architecture, these criteria included higher performance, lower power consumption, and pin-compatibility with the company’s C7 line of x86-compatible microprocessors. The result was a chip design with twice to four times the performance within the same package and power envelope.
The architecture’s execution pipeline is key to this performance. The C7 and most lowpower x86 designs have an in-order pipeline, while Isaiah goes with out-of-order execution found in higher-performance Intel and AMD solutions. Still, VIA needed to do things differently since this approach often results in higher performance but steeper power requirements. The pipeline design included micro-op fusion, which “fuses” two x86 instructions and executes them as a single micro-op. The system also decodes up to three instructions per clock. And, it can execute seven micro-ops per clock, including two integer, a load, a store address, a store data, a “media” SIMD SSEx, and a multiply micro-op.
VIA changes the care and feeding of the pipeline from the cache system (see the figure). It has a 16-way, 64-kbyte L1 cache, and its 1-Mbyte L2 cache is exclusive. This means that data will reside in only one spot within the caching system.
An L1 miss results in a parallel check of the L2 cache and data prefetch queue. A second-level miss pulls data directly from main memory into the L1 cache and subsequent data into the data prefetch queue. VIA designers tweaked the asynchronous prefetch mechanism to handle variable strides. This type of feature is found in higher-end x86 platforms. Likewise, the chip’s ability to drop a smaller data item into an incoming block to the prefetch queue is also an advanced technique not usually found in this class of processor.
While they were at it, the VIA designers completed a major overhaul of the floating-point unit. The result is faster execution than an Intel Core 2 Duo. The power-management section also got torn down and rebuilt for even more ACPI P-states and better power-management options, most transparent to the user.
Additionally, the power-management subsystem now can change voltage and clock faster through the use of dual phase-locked loops (PLLs). It also can take advantage of die temperature. A sensor enables the system to employ a lower voltage at lower temperatures and adjust the voltage as the temperature rises.
With this flexibility, the system can use overclocking when the die temperature is low for a performance boost without the risk of failure. It also would allow a 2-GHz version to run at a higher frequency, such as 2.2 GHz. The system can quickly switch between configurations by running the second PLL at the next higher voltage so a change can occur without resynching the main PLL.
Isaiah also continues to run the bus and the execution pipeline during a P-state transition, while most of the competition stops execution. It then makes sense to shift between PLLs in an incremental fashion until the desired power envelope is reached.
The C7 will continue to be available since it can hit lower power goals at a lower price. Isaiah garners a premium with a wider power and performance envelope. It retains C7 features such as AES encryption, SHA-1 and SHA-256 secure hashing, and random number generation. A new secure execution mode supports an on-chip volatile secure memory (VSM) area and encrypted instruction fetching. The VSM can be accessed using new instructions that are part of the new execution mode.
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