Maxim Integrated Products’ DS3102 clock timing IC monitors and generates clocks for Sonet/SDH, synchronous Ethernet (Sync-E), PDH, and wireless systems. It’s designed for full carrier-class Stratum 3 clock synchronization for G.8262-compliant synchronous Ethernet equipment. Typically, Stratum 3 cocks are synchronized by higher-stratum-level clocks in the hierarchal network timing topology used in the telecom industry. IETF standard Network Time Protocol RFC 1305 and Telecordia GR-1244 set these levels.
The DS3102 features two independent digital phase locked-loops (DSPLLs). One creates the main system clock, and the other generates the derived DS1/E1 clocks to send to an external Building Integrated Timing Source/Synchronization Supply Unit (BITS/SSU) through DS1/E1 transceivers (see the figure).
The DPLLs use DSP and digital frequency synthesis to implement clocks that are precise and flexible with consistent performance over voltage, temperature, and manufacturing process variations. Also, the DPLLs are digitally configurable for input and output frequencies, loop bandwidth, damping factor, and pull-in/hold-in range.
The device supports all common system clock rates for Sonet/SDH, Sync-E, PDH, and wireless standards. It can be designed into a variety of wired and wireless systems, including add-drop multiplexers, digital cross-connects, carrier-class switches, routers, wireless basestations, DSLAMs, and multiservice access nodes.
The DS3102 continuously monitors up to eight input clocks for activity and frequency. The device can automatically qualify or disqualify these inputs according to the highest-priority valid input. These inputs can be assigned to either of the two internal DPLLs. The eight inputs accept all common telecom clock rates as well as all multiples of 2 kHz up to 131.072 MHz and all multiples of 8 kHz up through 155.52 MHz (differential) and 125 MHz (single ended).
Also, the DS3102 can simultaneously generate a total of seven output frequencies plus 2- and 8-kHz frame pulses. Each output clock can be frequency-locked to either of the two DPLLs. The output clocks have the same frequency options as the input clocks, plus differential signal rates as high as 312.5 MHz. Internal programmable synthesis engines can generate any multiple of 2 kHz up to 77.76 MHz, any multiples of 8 kHz up to 311.04 MHz, and any multiple of 10 kHz up to 388.79 MHz.
The DS3102 comes in an 81-lead, 10- by 10-mm ball-grid array (BGA) package. It operates from 1.8 V with 3.3-V I/O and a serial peripheral interface (SPI) to the external processor. Prices start at $35.20 in 1000-unit quantities. A demo kit is available for device evaluation.
Maxim Integrated Products
www.maxim-ic.com
Reprints
