As an application engineer, I spend a lot of time convincing customers that a delta-sigma modulating analog-to-digital converter (ADC), or DSM, would be the best choice for their particular application. Then they come up with all sorts of excuses for why they prefer a successive-approximation ADC.
I’ve come to the conclusion that they prefer successiveapproximation ADCs because they fundamentally don’t understand how a DSM works, perhaps because DSMs involve both analog and digital design. This is unfortunate because, from a historical perspective, the DSM development has been gradual and straightforward to understand.
If you have a digital-to-analog converter (DAC), a comparator, and some logic, you can build an ADC. The logic determines how quickly the answer is resolved. A successiveapproximation register (SAR) uses logic to perform a binary search to quickly resolve the answer.
Back when logic was expensive, a cheaper though slower method was to connect a counter to a DAC. The only logic required was to reset the counter to zero and continuously increment it until the DAC value equaled the input voltage. This DAC/logic combination generates an analog ramp.
An analog integrator is a less expensive way to generate a ramp. In its simplest form, it consists of a current source and a capacitor. Charging the capacitor with a current source results in a ramp voltage:
When the reset is released, the current source charges the capacitor and produces a linear ramp that starts at zero and eventually reaches the value of the input voltage (Fig. 1). At this point, the comparator’s output goes low, and the input voltage is converted to a pulse width. Measure its width, and you know the input voltage. A reference clock can easily measure this time (Fig. 2).
When the reset signal is released, the counter increments on each clock cycle until the comparator output goes high and the counter is no longer gated. The rising edge of the reset line latches the data. The latch now contains the pulse-width value in counts. The relationship between the input voltage and value in counts is:
The number of counts is proportional to the input voltage. With a 1-nA current source, a 0.1-µF capacitor, and a 1-MHz clock, a 1-V input results in a 100 counts. This was a very popular ADC method in the early 1970s. Most likely, the current source would have come from Siliconix and the digital logic would comprise 74xx transistor-transistor logic (TTL) ICs.
SINGLE-SLOPE LIMITATIONS A single-slope ADC has several limitations. Any noise on the ramp of the input signal can cause jitter on the comparator transition, effectively limiting this type of ADC to eight to 10 bits of resolution. You can count the width with more than 10 bits, but the extra resolution would just be noise. More importantly, the accuracy depends on the tolerance of the current source (10%), the capacitor (5%), and the clock (0.1%).
This type of ADC must be calibrated. And because these component values change with temperature, it should be periodically recalibrated in operation. If this resolution is enough and the calibration is acceptable, then this is a perfectly fine ADC for your needs. It wasn’t for most applications, so new techniques had to be developed.
none of the text books do justice to the topic of dual slope conversion and DVM designs. The equations V(ramp) and n[count] as specified in the article definitely clarify and increase the comprehension of the underlying issue.
Anonymous -May 22, 2008
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