ED_EDA Alert Update_: Power Formats: You Can Have It Your Way
EDA Alert e-Newsletter |
April 1, 2008
ESC Silicon Valley: Learn Today, Design Tomorrow ESC Silicon Valley is where the global design engineering community gathers to learn, collaborate and celebrate innovation. ESC is celebrating 20 years of educating the creators of technology at the San Jose Convention Center from April 14 - 17 with over 350 exhibiting companies and over 200 new courses to this year's conference. Register today! Use Code: UX2-D
viewpoint
Power Formats: You Can Have It Your Way
By Dave Allen, Atrenta Inc.
Now that there are two competing industry formats to capture power intent for low-power designs—the Common Power Format (CPF) and the Unified Power Format (UPF)—design teams need to understand the similarities and differences between the two.
Our editors have been busy! Come read their commentaries and check out exclusive videos from the Mobile World Congress, APEC, and Embedded World exhibitions and see the technology of tomorrow from major players in the electronics industry.
engineering tv
Festo MPS System: Part 1
At the Vincent A. Stabile Laboratory at NJIT's Newark College of Engineering, a companion robotics laboratory features 10 experimental stations, the Festo System, which gives students "hands-on" training in solving practical problems using robotics for today's automated manufacturing. In this interview, Sanchoy Das, a professor in the Department of Industrial and Manufacturing Engineering, provides Engineering TV with an overview of the Festo MPS and how it has contributed to their student's understanding of automated manufacturing systems.
Synthesis Tool Revamped To Avoid Routing Congestion
By predicting circuit congestion "hot spots" early in the design flow, Synopsys' Design Compiler Graphical synthesis tool helps RTL designers avoid problems during the detailed routing of their systems-on-a-chip (SoCs). The tool provides visualization of the congested circuit regions and performs synthesis optimizations to minimize congestion in those areas.
Almost all chip designs go through engineering change orders (ECOs) to implement late-stage design modifications due to changes in design requirements or incorrect logic function. Engineering and management recognize ECOs as a time of high stress and long hours of manual work, which lead to uncertainty in schedule, cost, and functional correctness.
Designers of electrical equipment, such as motors, actuators, transformers, and other electric and electromechanical systems will find a myriad of uses for two tools from Ansoft. Version 12 of the company's Maxwell electromagnetic field simulation software includes a 3D electric transient solver that solves time-varying electric fields due to a transient disturbance, such as lightning strikes on electrical equipment.
Joint System-Level Design Flow Moves To Second Generation
A joint electronic system-level (ESL) design flow forged by CoWare and Sonics has been upgraded to its second-generation incarnation. The flow, which combines Sonics' system-level interconnect IP technology with CoWare's virtual platform technology, gives designers advanced debugging and analysis capabilities for platform architecture design and platform verification.
ESC Silicon Valley: Learn Today, Design Tomorrow ESC Silicon Valley is where the global design engineering community gathers to learn, collaborate and celebrate innovation. ESC is celebrating 20 years of educating the creators of technology at the San Jose Convention Center from April 14 - 17 with over 350 exhibiting companies and over 200 new courses to this year's conference. Register today! Use Code: UX2-D
quick poll
Last month, Fujitsu announced a 2.5-in. hard-disk drive with speeds up to 7200 rpm and a 320-Gbyte capacity, using just 2.3 W. What does this indicate about the role of HDDs in the future?
The HDD is here to stay.
Competition with flash will balance both technologies.
Flash's dominance is inevitable.
Eventually, both technologies will be replaced by more exotic storage.
Click here to take the poll. Remember to scroll down, the poll is at the bottom of the page.
engineer's resource
Webinar: Improving The Accuracy Of Eye Pattern Measurements Presented by LeCroy April 9 at 2 pm ET
This Web seminar, presented by LeCroy Business Development Manager Michael Schnecker, will describe the limitations of eye-pattern testing and some of the more important eye-based measurements. A measurement technique using the normalized q-scale method from jitter analysis and expanded to two dimensions will be described, and its application to mask testing and signal measurements will be demonstrated.
ESC Silicon Valley: Learn Today, Design Tomorrow ESC Silicon Valley is where the global design engineering community gathers to learn, collaborate and celebrate innovation. ESC is celebrating 20 years of educating the creators of technology at the San Jose Convention Center from April 14 - 17 with over 350 exhibiting companies and over 200 new courses to this year's conference. Register today! Use Code: UX2-D
ED bookstore
FPGA Prototyping By VHDL Examples (Xilinx Spartan-3 Version)
By Pong P. Chu
There's three parts to the book. Part 1 introduces elementary HDL constructs and their hardware counterparts. It demonstrates the construction of a basic digital circuit with these constructs. Part 2 leads into applying the techniques from Part 1 to design an array of peripheral modules for a prototyping board. It's recommended to anyone looking to get started with FPGA prototyping using VHDL. Just make sure you bring a little foreknowledge of VHDL and HDL constructs in general to the table.
Reprints
