ED_EDA Alert Update_: 45th DAC Takes The SoC Methodology Plunge
EDA Alert e-Newsletter | June 3, 2008
EVE - UNDISPUTED HW/SW CO-VERIFICATION WORLWIDE LEADER
HDL-Acceleration, C/C+/SC/SV Cycle-Level Acceleration, C/C++/SC/SV Transaction-Level Acceleration and In-Circuit Emulation from 10 to 100 times more efficient in $/cycle than any other solution on the market Automatic compilation of up to 300M ASIC gates from SV/Verilog/VHDL RTL/gates, interactive multi-layer hardware/software debugging, ESL emulation. Verify your hardware, integrate your hardware/software, validate your entire software before tapeout. One vendor, one support organization.
At the inaugural Design Automation Conference in 1964, then known as the SHARE Design Automation Workshop, the fledgling design-automation industry batted around some of the fundamentals of its mission to engineers. Papers carried titles such as “A method for best geometric placement of units on a plane,” and “New horizons in graphic output on the IBM 1403 printer.” Some of that year’s program hinted at yet unformed methodologies. Now, as the EDA industry heads for the 45th Design Automation Conference (DAC, Anaheim, Calif., June 8-12), the focus is squarely on methodology.
Our editors have been busy! Come read their commentaries and check out exclusive videos from the Embedded Systems Conference, Mobile World Congress, APEC, and Embedded World exhibitions and see the technology of tomorrow from major players in the electronics industry.
Aftermarket battery packs are available for most portable devices. Hosted by Robin Sarah Tichy, Technical Marketing Manager with Micro Power and contributor to Electronic Design's Power Design column, this webcast will present the results of several product tear-downs on aftermarket battery packs and explain how substandard aftermarket packs can cut corners on cost, safety mechanisms, and battery performance.
Webinar: Supercharging Products with Embedded RFID Sponsored by SkyeTek | June 26 @ 2 pm ET They may still look the same on the outside, but embedded RFID readers and software can transform products from the inside, offering manufacturers, OEMs, and product designers new opportunities for competitive advantage through increased efficiency, accuracy and product differentiation. With an seemingly unending list of products, RFID is a key technique to adding new functionality, increasing reliability and enhancing the user experience. At this webinar and interactive Q&A session learn the difference between RFID and existing barcode and contact technologies; and how embedded RFID has new applications in disposable authentication, smart shelves and cabinets, contactless payments, tracking, inventory and stock, and customizable configurations. Also catch up on unique technical and business considerations for embedded RFID and companies that are already implanting the technology.
Rev up fuel efficiency and win $10,000 Take the "green challenge" and design a solution using Infineon products that enables or improves energy efficiency for automotive applications. You could win the grand prize of $10,000, second prize of $5,000 or third prize of $2,000.
The Cyclone Waste Heat Engine (WHE) is a self-starting engine that operates in a low-pressure, low-temperature range. The engine runs on waste-heat emanating from an external source such as exhaust from an internal/external combustion engine or the direct burning of biomass. The WHE is also designed to run efficiently on solar heat without the installation of costly photovoltaic panels. This technology, according to Cyclone, can be implemented in the automobile, solar panel, and the power-generator industries. Also, excess electricity could be directed back to the power grid for electrical power credits.
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EVE - UNDISPUTED HW/SW CO-VERIFICATION WORLWIDE LEADER
HDL-Acceleration, C/C+/SC/SV Cycle-Level Acceleration, C/C++/SC/SV Transaction-Level Acceleration and In-Circuit Emulation from 10 to 100 times more efficient in $/cycle than any other solution on the market Automatic compilation of up to 300M ASIC gates from SV/Verilog/VHDL RTL/gates, interactive multi-layer hardware/software debugging, ESL emulation. Verify your hardware, integrate your hardware/software, validate your entire software before tapeout. One vendor, one support organization.
Floorplanner And Prototyping Platform Takes Lead From Specification
Called the first tool of its kind on the market, Javelin Design Automation has launched its j360 tool suite, a specification-driven virtual-silicon prototyping platform and floorplanner. Javelin’s j360 is said to realistically predict and optimize designs for implementation feasibility and quality-of-results (QoR) in parallel to their design development at the electronic system-level (ESL), register transfer-level (RTL) and netlist stages of design.
The HAPS-51T, a new addition to the HAPS (high-performance ASIC prototyping system) product family, leverages Xilinx's Virtex-5 LX330T devices to embody a suitable prototyping system for applications using high-speed serial interfaces like PCI Express, SATA, and Gigabit Ethernet.
Tool Closes Verification Loop Between ESL And Implementation
In addition to providing methodological guidelines, Iman’s book helps users learn the SystemVerilog language, and covers use of SystemVerilog and the OVM library for building a verification environment for a realistic design example. It packs more than 500 pages of original technical content, none of which duplicates the documentation already available on OVM World.
Step-By-Step Functional Verification With SystemVerilog and OVM
By Dr. Sasan Iman
In addition to providing methodological guidelines, Iman’s book helps users learn the SystemVerilog language, and covers use of SystemVerilog and the OVM library for building a verification environment for a realistic design example. It packs more than 500 pages of original technical content, none of which duplicates the documentation already available on OVM World.
EVE - UNDISPUTED HW/SW CO-VERIFICATION WORLWIDE LEADER
HDL-Acceleration, C/C+/SC/SV Cycle-Level Acceleration, C/C++/SC/SV Transaction-Level Acceleration and In-Circuit Emulation from 10 to 100 times more efficient in $/cycle than any other solution on the market Automatic compilation of up to 300M ASIC gates from SV/Verilog/VHDL RTL/gates, interactive multi-layer hardware/software debugging, ESL emulation. Verify your hardware, integrate your hardware/software, validate your entire software before tapeout. One vendor, one support organization.
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