VHDL Code Offloads LED Blinking Task To A CPLD

An earlier Idea For Design (Hardware-Based LED Blinking Control Eliminates Software Overhead) described a very interesting way to offload the software overhead required for a microcontroller to drive LEDs that indicate operating states to the user. That article discussed the use of memory-mapped LED control registers, buffers, and a clock source, all used to blink an LED without burdening the microcontroller code with the task.

This article expands on that Idea For Design, discussing how to implement a hardware-based LED driver in a complex programmable logic device (CPLD) using VHDL code. To do this, the designer simply needs to write VHDL code that implements the basic idea in the earlier Idea For Design.

Through the use of register-based control signals and an external clock source, the designer can configure the CPLD to blink a single LED or multiple LEDs at any desired rate or duty cycle. The components of the VHDL code can be stated simply:

• External Clock Source (f)—supplied by a microcontroller or external source
• Counter (n-bit)—incremented using the external clock source in order to blink the LED
• Multiplexer—used to control which counter bits are used to drive the LED
• LED Buffer—used to turn the LED on and off regardless of the state of the Multiplexer
• Combinatorial Logic—Used to combine any number of the n counter bits to drive the LED
• Address/Data Buses—buses used to write to the register-based Multiplexer and LED Buffer control signals
• Power-On Reset—signal used to reset everything on power-up

The figure shows a simplified block diagram that illustrates how the VHDL code is implemented. The equation that governs the 50% duty-cycle blink rate of the LED is:

where n = number of counter bits and f_CLK is the clock frequency.

For example, if a 32.768-kHz clock source was used in conjunction with a 16-bit counter and the LED is sourced from the 16th bit of the counter, the pulse width would be approximately one second. This would equate to a 0.5-Hz blink rate.

For more complex blinking rates, the designer can multiplex and combine multiple bits of the 16-bit counter combinatorially to drive the LED output at different rates and duty cycles. The VHDL code provided with this article (“VHDL Code Listing” at www.electronicdesign.com, Drill Deeper 19222) is an example of one way to implement the LED driver in a CPLD. However, the designer must consider the maximum frequency (blink rate) of the specific LED used, as well as the maximum frequency perceived by the end user.