[Technology Report]
DSP Advances Tackle More Complex Audio Algorithms
As digital audio algorithms get more complicated, DSP architectures are evolving to keep pace.
Digital audio basically started with the introduction of the CD music format. Since then, digital music and audio recording and playback have overtaken analog audio storage and playback as the dominant technology. Advances in DSP performance and continually decreasing DSP chip prices have both played enormous roles in making this possible.
But the audio algorithms that encode and decode the digitized music are constantly improving. These enhancements, along with new audio formats—ranging from the basic 2× CD sampling to Real Audio, Windows Media Audio, MP3, THX, and others—continually challenge the DSP engines. They must handle ever more complex algorithms that deliver better quality audio, reduce the number of bits per audio file, and offer additional features, like reverb and 3D spatialization.
Processing basic CD audio requires 10 to 20 MIPS of DSP horsepower, while MP3 music algorithms need between 20 and 30 MIPS. Some newer algorithms, which reduce the number of bits necessary to store and reproduce the music, take more complex computations and more compute power—typically 50 to 100 MIPS.
Achieving 20 MIPS or so on a dedicated DSP chip or an embedded DSP core, or even on a CPU with some DSP assist logic, is relatively easy for chips fabricated with mainstream 0.25-µm and smaller design rules. The DSP engine can handle all of the algorithms for standard CD and MP3 playback. The remaining functions a player typically needs include button control, housekeeping, motor control, and display management. Such functions were initially implemented in a more control-oriented device, like a microprocessor or microcontroller.
Some DSP chips—including the TMS320C25x and the new TMS320-DA250 series from Texas Instruments (TI), the DSP56F807 and DSP56852 from Motorola, and the ADSP219x family from Analog Devices—feature control-oriented instructions, enabling a single-chip solution. These chips can tackle the motor control functions in a CD player, or other tasks.
Yet the era of standalone DSP chips for the low-end systems is fading as system-on-a-chip (SoC) integration lets designers combine the DSP and control processor, and often the digital-to-analog conversion, mixed-signal output circuitry. New, improved DSP or CPU cores give designers a wide range of performances from which to choose. Some embedded CPU cores, like those by Advanced RISC Machines (ARM), ARC, Hitachi/STMicroelectronics, Tensilica, and others, offer DSP enhancements like a hardware multiplier-accumulator (MAC) or a DSP coprocessor to help speed the computations.
Over the last few years, the number of suppliers of standalone DSP chips has been reduced to just three main contenders: Analog Devices, Motorola, and TI. Intel Corp. and Analog Devices have co-developed a new 16-bit architecture called Blackfin, while Motorola and Agere Systems have teamed up to develop the STARcore architecture.
Earlier this year, Infineon decided to halt work on its proprietary Carmel DSP technology and join Motorola and Agere as a third partner on STARcore. Infineon will add the intellectual property (IP) developed for Carmel to the pool of resources for future STARcore development. Hitachi Semiconductor and STMicroelectronics have pooled efforts to extend the Hitachi-created SH processor family into the DSP space. The SH3DSP and SH4DSP processors have resulted from this collaboration.
Several companies offer DSP engines as licensable blocks of IP. As previously mentioned, ARM, ARC, and Tensilica have embeddable CPUs with DSP enhancements (the ARM9D, ARCtangent, and Vectra, respectively).
Other offerings include a family of cores from the DSP Group (the Oak, Pine, Teak, Teaklite, and the just released Cedar) and an extensible core dubbed Saturn from Adelante. Several companies feature a number of building-block cores, like the BOPS MAN array, Improv Systems' Jazz core, the LSI Logic LSI402ZX and 403LP (based on the ZSP architecture that LSI acquired by purchasing ZSP Corp.), and the 3DSP Corp. SP-3, -5, and -20 cores. (To learn more about configurable DSP engines, read "Reconfigurable Architectures Chart A New Course For DSPs," Electronic Design, Aug. 5, p. 46, or view the archives at www.electronicdesign.com.)
In addition to generic DSP chips, several companies have developed application-targeted chips for the multimedia market. Cirrus Logic crafted the CS494xx series of single-chip audio processors for mid- to high-end equipment in the home entertainment industry, the CS493xx series for the mid-range, and the CS492xx series for entry-level entertainment equipment. For the portable entertainment market, the company just recently introduced a low-power chip targeted at low-cost multiformat CD players (standard CD audio, MP3 audio, and Microsoft WMA audio), the CS7410.
The most recent addition to the entertainment-centric family, the CS49400 fits AC-3 and APP audio applications. Its custom Harvard architecture DSP engine has dual 32-bit MACs and 72-bit accumulators that can perform over 500 Moperations/s. (The large accumulators help minimize distortion due to round-off errors that could occur if smaller word lengths were used.) Software downloads configure the audio processor and allow it to support all standard encoder formats. A pulse-code-modulated (PCM) processor executes DSP algorithms for tone control, parametric and graphic equalization, bass management, delay insertion, volume control, and much more.
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