High-Performance Processor Interconnect Gains Wide Support HyperTransport (HT) is on its way to widespread use in embedded systems. It is the chosen interconnect for a number of new processors, such as Broadcom's (www.broadcom.com) BCM1400 and AMD's (www.amd.com) Opteron. There is also a large collection of bridge and interface devices with HyperTranport links like PLX's (www.plxtech.com) PowerDrive HT7520 Tunnel-to-Dual PCI-X Bridge and SiPackets' (www.sipackets.com) SP1011 PCI bridge.
HyperTransport provides a high-speed interconnect for processors, memory, and devices. The standard defines a tunneling architecture whereby a HyperTransport device will forward packets not destined for the device. In a one-processor system, data moves through a daisy chain of HyperTransport devices. Bridges provide access to ports like a PCI-X bus. This highlights HyperTransport's complementary nature with other interconnect standards such as PCI-X, InfiniBand, and PCI Express. More complex HT architectures are possible if the number of HT links is increased to more than two. Communication systems can be created where packets are passed through a daisy-chain architecture. Additional processing or routing is possible using the third link. Links can often be configured for an SPI-4 Phase 2 interface
HyperTransport multiprocessor shared memory implements a nonuniform memory access (NUMA) architecture. Coherent and noncoherent caching is supported.
The standard covers a range of details from error recovery to power management. For details, check out the HyperTransport Consortium's Web site, www.hypertransport.org.
Simple Interface, Low Pin Count HyperTransport uses two unidirectional links plus power and control lines. The bus width and bandwidth scale as expected, but the pin count grows a little differently because of the additional power (and ground) lines included as the number of data pins grows.
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