If your system's signal processing requirements in-clude peak detection and amplification, consider a simple circuit that will satisfy both needs and save hardware.
The single-supply circuit shown in the figure is an inverting peak detector with programmable gain. Its peak detector is basically an inverting amplifier configuration whose gain is established by the ratio of the wiper-to-high (R2) and wiper-to-low (R1) resistances of the CAT 5113 digitally programmable potentiometer (DPP). A 100-tap potentiometer, the DPP provides programmable circuit gains from 1/98 to 98.
Although op amps A1 and A2 are cascaded to form the open-loop gain, the primary function of the unity-gain A2 is to buffer the voltage stored across C1. Because half of the gain values are less than one, the circuit can be used as a peak detector with attenuation. The output voltage for this circuit is:
VOUT = (R2/R1)VIN (pk) = [(1p)/p]VIN (pk)
where p represents the relative wiper setting from one end of the potentiometer (0) to the other (1) end.
The standard hardware requirements for sample-and-hold and peak detector circuits apply to D1, C1, and A2. C1 must be a high-quality capacitor, D1 must be a low-leakage diode, and the bias current of A2 must be low.
A solid-state switch can be used as a reset for the detector. Both the gain and reset functions can be computerized if this switch and the potentiometer are driven by processor-generated signals. The measured performance of the circuit is in the order of 1%, or an LSB of the potentiometer.
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