The latest Spice transistor models contain provisions for modeling the complex junction characteristics. They can even extend the simulations to include RF performance. In many ways, the CMOS transistor is moving toward the performance of an ideal device—a wire with gain. Certainly, the physical dimensions are closing in on a zero-dimensional device, although we will always have to use at least a few atoms to make an active device.
Even though the new BSIMs (Berkeley short-channel IGFET models) have added parameters to characterize the high complexity of nanometer processes, these versions have far fewer anomalies and forced curve-fitting functions. The many deep-submicron effects all have modeling parameters, most of which actually reflect the underlying physical construction.
These BSIM 4 models are focused on the 130-nm and smaller CMOS transistors. Even those transistors without the analog process modules offer excellent gain and linearity. Usable device bandwidth now spans the frequency range from dc to 10 GHz. Certainly, designs become less difficult when gain and bandwidth aren't constraints, although designers always want infinite gain and bandwidth at zero power.
The conundrum is that these device characteristics continue to improve, but at the cost of a very reduced operating range. Obviously, modeling a device over a very small operating range is much more linear and accurate than trying to model device characteristics that are supposed to scale across many process boundaries and dimension ranges.
As the devices scale to smaller dimensions, the voltage fields in the oxides grow to exceed the safe operating limits of the materials. The thinner oxides require reductions in operating voltages to minimize field-induced oxide breakdown, while creating the "free" benefit of reducing operating power.
This lower voltage complicates the design process. An issue with lower voltages is that the active devices may be operating at a subthreshold level, increasing leakage currents. One solution is to move to an active substrate biasing scheme, which means that substrates also become an active circuit element. The designer must add some function to the design that will change bulk biasing as a function of the absence or presence of signals.
Lower operating voltages require new architectures and circuit to-pologies to enable any dynamic range at all. As the processes continue to scale, eventually to atomic dimensions, we should see operating voltages of less than 0.5 V. At that supply level, outputs with a rail-to-rail swing of a few hundred millivolts mean that it will become harder to work with signals. Many parameters might become irrelevant when signals, supply, and noise are all measured in the same units.
In the final limits, transistors will become ideal devices, occupying zero space and producing infinite gain with infinite bandwidth. But unfortunately, they will do so only with signals that feature 0-V swings in a 0.1-V supply. A more realistic endpoint would be for the magic mix of high-k, low-k dielectric, 3D devices to provide good gain and bandwidth while continuing to operate on at least 1-V supplies.
The very fine line processes are producing excellent devices for high-performance circuits. Fortunately, the models for these devices also are improving at the same rate.
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