[Product Innovation]
100-MIPS Microcontroller Brings Precision Analog To Control Systems
New microcontroller merges on-chip high-resolution ADCs and DACs with 8051 core and flash memory for speedier applications.
A myriad of sophisticated control systems are emerging with demanding requirements for high-speed precision digital and analog performance. Cygnal Integrated Products addresses these demands with a 100-MIPS 8051 microcontroller (MCU) chip with two 8- and 12-bit analog-to-digital converters (ADCs) and two 12-bit digital-to-analog converters (DACs) that feature superior noise and distortion performance.
The C8051F120 CMOS chip contains other high-performance analog functions too. For instance, an analog multiplexer, programmable gain amplifiers (PGAs), two comparators, a precision voltage reference, a temperature sensor, a programmable oscillator, and a precision VDD monitor/brown-out detector are available (Fig. 1).
Cygnal's development follows the trend of combining pure analog and mixed-signal functions with 8- and 16-bit MCU cores and memory on one chip. This cuts the size, cost, and power-dissipation levels of new MCU products. They tend to merge high-speed digital circuitry with high-resolution data converters and precision analog circuitry on the same chip. These devices also incorporate flash memory for maximum flexibility and in-system programmability.
Earlier-generation 8051 microcontrollers combined high-performance analog functions on a single silicon die, but these chips traded higher analog performance at the expense of digital performance. Cygnal's latest introduction changes this entirely. Now designers can maintain a high level of precision analog functionality in a 100-MHz digital environment.
The company carefully managed the analog and digital clocks to minimize the chance of digital interference affecting a critical analog decision. It separated the most egregious digital functions, specifically the flash and static memories, from analog circuits as much as possible. Furthermore, analog signal paths are fully differential with a high power-supply rejection ratio (PSRR) to minimize interference and coupling of power-supply noise into the signal path.
Clever Design Approach: The C8051F120 includes a 12-bit successive-approximation register (SAR) ADC with guaranteed 12-bit accuracy at a sampling rate of 100 ksamples/s, while maintaining integral nonlinearity (INL) and differential nonlinearity (DNL) within ±1 LSB. This performance is due to the use of a clever resistor string and charge redistribution.
Likewise, the signal-to-noise plus distortion performance of the ADC is rated at 66 dB. The two on-chip voltage output DACs offer 12-bit resolution with an output settling time (full-scale) of 10 µs. The DACs are matched in speed to the ADC with a DNL of ±1 LSB and an output-voltage range of 0 to VREF −1 LSB. Separate voltage references for the DACs, and the 12-bit ADC, allow the C8051F120's users to implement a DAC as a gain-correction unit for the 12-bit ADC.
An additional on-chip ADC—a true 8-bit unit—features a maximum sampling rate of 500 ksamples/s, an eight-channel input multiplexer, a PGA, and comparators. With this extra ADC, a designer can accomplish noncritical housekeeping chores, relieving the higher-resolution ADC to perform more critical tasks. All of the chip's data converters are configured by software via special function registers. The low-power comparators provide 4-µs response times with 100-mV overdrive.
Instruction Pipelining: With its enhanced core structure, the new MCU has nearly quadrupled its processing abilities, while maintaining code compatibility with the 8051 instruction set. It achieves a 100-MIPS throughput with a 100-MHz clock.
Although the C8051F120 MCU core operates at 100 MHz, its flash memory is limited to 25 MHz. This isn't an issue, however, because of the prefetch queue and cache that Cygnal put in the design. Essentially, the flash is read in 32-bit words (4 instruction bytes) at 25-MHz speeds, and the instruction decode is fed 8-bit bytes at 100 MHz. Most instructions are 1 or 2 bytes, achieving 100-MIPS performance (Fig. 2).
For sequential program execution, the prefetch buffer is deployed. If the next instruction is out of sequence due to a jump or call, then the cache is checked. When available, the cache word containing the instruction is used, with subsequent words ac-essed through the prefetch queue.
This means that the cache only needs to hold single words, rather than entire sequences of instructions as in a typical instruction cache. Very tight loops may be maintained within the cache. But only the first few instructions are necessary.
However, if the next instruction is not in the cache, a delay occurs until the required word is read from flash. The typical cache hit rate is above 90%. Both cache operation and hardware debug support are transparent to the software.
Tracking De Bugs: Tracking down bugs on this MCU doesn't mean pulling out an expensive in-circuit emulator (ICE) unit. Instead, the chip contains a JTAG interface, hardware breakpoints, and a limited trace capability that together streamline debugging and reduce debug development hardware costs. In-device testing only requires an inexpensive JTAG interface, which is offered in the development kit.
The trace support is limited to saving the instruction pointer and the tracing stops when a hardware breakpoint is hit. Then the trace buffer holds the instruction addresses that led up to the breakpoint. In fact, the trace buffer actually stores the instruction pointer for any branch, call, or interrupt and is available upon any halt of the CPU.
Although the C8051F120 has a top speed of 100 MHz, its phase-locked loop (PLL) and internal clock controls are more flexible, enabling program control of the clock speed. A lower clock rate reduces power consumption (a desirable feature) without having to go into the sleep mode. The internal oscillator operates from 2 to 25 MHz at 2% accuracy, but the faster speeds require an external crystal or clock.
The internal RAM contains the typical 8051 scratchpad of 256 bytes plus an additional 8 kbytes of RAM. Off-chip memory can be accessed as well.
Common digital peripherals can operate at 100 MHz to keep up with the processor core. Making up these peripherals are 64 general-purpose I/O ports, SMBus/I2C, SPI, and dual serial ports. All counters are 16-bit types. There's a dedicated watchdog timer and the reset line is bidirectional, permitting the processor to reset external peripherals.
A crossbar system lets various peripherals be connected to selected I/O pins. Moreover, the MCU is designed for a 2.7- to 3.6-V supply range. The digital I/Os are 5-V tolerant. There also are 22 vectored interrupts.
Price & Availability Implemented in a 0.35-µm, four-metal-layer CMOS process, the C8051F120 will be sampled in June, with production slated for the third quarter. The C8051F120 comes in a 100-pin TQFP, and the C8051F121 is housed in a 64-pin TQFP package. In 1000-piece quantities, the C8051F120 and C8051F121 are priced at $18.75 and $17.82.
A development kit is in preparation too, including a development board, all IDE software, evaluation C compiler, and RS-232 to JTAG serial adapter. It will be available in June as well for $149.00.
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AVINASH -March 23, 2007 (Article Rating: )
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Sudarshan -July 13, 2003
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