With the explosion in communication and consumer products, analog design is looming large. However, analog designers—and tools to enhance their productivity—are in very short supply. Development of the analog segments of sophisticated designs may take longer than the digital portion, even though the analog portion is often smaller. Meanwhile, digital designers have synthesis, formal verification, and test pattern-generation tools, among others, at their disposal. They also can create large circuits from high-level languages.
So how can greater productivity be achieved in analog design? The highly anticipated solution will let designers synthesize analog and mixed-signal circuits. But until this capability is developed, designers must rely upon evolving answers to the analog challenge.
Design tools are needed to address two different areas: the analog portions of analog/mixed-signal (A/M-S) designs; and fast, low-voltage digital circuits that exhibit analog effects. The former appears to be where IP (design reuse) and synthesis can boost productivity most dramatically. I say "appears to be" because the bottom-up methodologies currently employed by analog circuit designers are inconsistent with the adoption of higher-level design tools, which support a top-down methodology.
The downside to using top-down approaches in the analog realm is that they require a paradigm shift in the way that analog circuits are typically designed. Before top-down analog tools gain wide acceptance, their users must expand their traditional schematic-based orientation to include the language-based orientation necessary to take full advantage of such tools. Unfortunately, most engineering schools aren't yet teaching this language orientation.
Setting aside these considerations of approach and orientation, it seems clear that the effective use of IP can help to address the shortage of qualified analog designers. In fact, one current analog-design approach enables capabilities that resemble "soft" IP. While falling short of full synthesis, it allows the creation of key design aspects via parameterization. This means that the designer can alter some design specifications, resulting in design parameters that are changed automatically.
But IP has its downside. Conventional wisdom holds that it requires about an order of magnitude more time and effort to create and document a design with reuse as a goal than it does to produce the same design for one-time use. Thus, IP in A/M-S designs delivers a relatively low rate of return. Further, if verification of the modified design is to be avoided, IP is only viable when changes are minimal.
On the other hand, synthesis isn't as far along as the use of IP. A handful of tool vendors are working to bring synthesis to fruition by developing tools that address one or more of the three major phases of synthesis: topology creation, design optimization, and design layout. With such tools in early development at this time, their promise is still largely latent.
With respect to high-speed, low-voltage digital designs, the primary issue is that such circuits actually behave like analog circuits. In these designs, analog effects must be considered both inside and between the blocks. Interconnects need to be modeled as coupled-resistor-capacitor networks. Long circuit paths lead to inductive effects that are difficult to find, analyze, and fix. Some signal-integrity analysis tools are relatively mature and adequately identify the presence of signal-integrity problems. But today's solutions for addressing these challenges are incomplete. Current tools don't provide comprehensive resolution strategies, much less automated solutions to the problems.
The prognosis for progress is mixed, as we're working through a period of transition in our profession. A/M-S design methodologies need to change so that designers recognize and take advantage of the capabilities of the tools now becoming available. Standard languages won't be widely adopted until a critical mass of libraries exists to support them. Development of these model libraries could take as long as five more years. Analog synthesis tools will come in due time.
Short of these paradigm shifts, tools may emerge that enable IP to be more readily used. This can be achieved by removing some overhead associated with its creation, or by leveraging latent IP in existing topologies, specifications, testbenches, and simulation strategies.
If you want to learn more, we invite you to explore the developments in A/M-S design during paper sessions at the 39th Design Automation Conference in New Orleans this June 10-14. Or, visit the exhibit floor.
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