Handsets employing 3G wireless, and beyond, are expected to have a large number of new features and functions, such as MPEG-4 video and audio. These compute-intensive tasks place major demands on digital signal processors (DSPs)—the IC workhorse of conventional wireless and mobile communications designs. Requirements include higher performance, considerably lower power consumption, small silicon area, low cost, architecture flexibility, and faster time-to-market.
Facing these demands, designers can easily conclude that power-hungry DSPs with conventional instruction-based architectures don't suit next-generation mobile and wireless handsets. This calls for a paradigm shift to a new class of IC—the adaptive-computing machine (ACM).
To illustrate the basic design tradeoffs and deficiencies a DSP poses, consider the baseband processor of a wireless handset. The baseband processor comprises a general-purpose RISC microprocessor, one or more DSPs, and one or more ASICs. To help minimize design cost (and the cost of finished silicon), it's prudent to execute as much functionality as possible on the DSP. But there's never as much DSP processing power as needed. This lack of power will become more problematic for the growing computational demands of future 3G and 4G handsets.
Consequently, design decisions are made about which portions of the design execute best in the RISC microprocessor, DSP, and ASIC portions of the system. The goal is to perform the least amount of the design in an ASIC because of its long, difficult, and costly design, test, and fabrication process. If errors happen in the implementation, or in the original algorithm, an ASIC provides no ability to correct problems in the finished design without significant delays for redesigning, retesting, and processing new silicon.
Additionally, errors occurring early in the design process significantly affect system performance, IC cost, total development cost, and ultimately, time-to-market. Fortunately, an ASIC supplies more processing power than a DSP for the specific algorithm implemented. An ASIC also is more efficient in terms of power consumption than a DSP. So, allocating tasks to an ASIC can prolong battery life.
There are DSP design considerations too. The goal is to load the DSP with as much computation as possible. But during the design-partitioning stages, a designer can only estimate the computational requirements (MIPS) each algorithmic element will demand from the DSP. The exact level of MIPS is unknown until the C- or assembly-language programs are written.
Limited Choices Available: Two design choices exist if the estimate is low, or if the DSP doesn't have the predicted processing power. One is to include a second DSP, and the other is to assign more of the design to the ASIC. Both options lead to an IC redesign. Furthermore, a DSP can't effectively perform certain algorithms due to its lack of power or flexibility, such as motion estimation, discrete cosign transform (DCT), and Viterbi decoding. These are usually assigned to an ASIC.
Although DSPs are becoming more powerful, frequently they still can't keep pace with the computing demands placed on them. In many cases, ASICs may be the only choice available to implement most 3G air interface requirements. However, many 3G techniques, like adaptive encoding and modulation schemes, aren't well suited for ASIC implementations.
These techniques don't constitute a single algorithm, which makes for a compact ASIC design. Instead, they involve a wide range of algorithms, selectable according to the type and volume of transmitted traffic and channel conditions existing at each instance in time. These multiple algorithms dramatically speed growth in the amount of ASIC silicon required.
The adaptive-computing machine referred to earlier introduces a more efficient way to implement 3G (and beyond) wireless and communications designs. Its architecture uses CMOS silicon more efficiently to extend computing performance beyond conventional methods. In adaptive computing, algorithms are mapped directly onto dynamic hardware resources. This technique gives the designer the most efficient use of hardware in terms of cost, silicon area, performance, and power consumption.
In an adaptive-computing chip, the vast majority of gates is employed to solve the computational problem. The control circuitry consumes a minority of the chip's total gates. In contrast, a DSP uses about 5% to 10% of its gates for actual tasks, while the other 90% goes toward the control overhead of decoding and managing instructions.
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