Greater computational complexity and the rising broadband demands of the evolving third-generation wireless standards are forcing developers to look beyond traditional digital signal processor (DSP) architectures. Since MOPS requirements for these applications are increasing faster than Moore's Law, conventional DSPs need expensive ASICs to supply the additional processing horsepower needed.
While the combination of a traditional DSP and an ASIC meets the requirements, it is expensive. First, it is a single-threaded architecture supporting multithreaded processing, states Marc Ostrowski, product marketing director at Morphics Technology in Campbell, Calif. Second, he continues, it requires expensive cache and hardware to manage shuttling of data off-chip between the ASIC and the DSP.
To surmount these limitations and provide an optimized dedicated processor for 3G baseband processing, Morphics has developed a distributed dataflow-architecture with parameterizable datapaths and function-specific DSPs. These datapaths deliver the efficiency, scalability, and flexibility demanded on a channel card. They also enable the basestation designer to program its proprietary estimation algorithms. In essence, it is an integrated hardware/software architecture that provides a high-level programming interface (see the figure), the virtual machine interface (VMI).
To support software development for the 3G basestation processor (3G-BP), the VMI provides an object-oriented programming interface be-tween the basestation processor hardware and the layer 1 control software. According to the company, the VMI is generic across 3G air interface standards and is hardware independent. It is supplied as a library of C-based software objects that reside on the control processor along with the layer 1 software.
The first member of this programmable wireless signal processor family is the 3G-BP64, designed to handle up to 64 W-CDMA channels. It performs all the baseband receive- and transmit-channel processing needed on a channel card between the digital antenna interface and the channel codec function, for up to 64 channels.
Four primary processing units on this chip perform rake receiver functions, including parameter estimation and finger combining, as well as searcher, preamble detection, and transmitter functions. In essence, these processing units search for new mobiles, find new paths for mobiles they are already tracking, and perform data demodulation and detection on the receive path, while doing data modulation on the transmit path.
Other features on-chip include an antenna selection interface, an uplink/downlink codec in-terface, a control processor interface, and a glueless interface to the Motorola 60X bus.
Packaged in a 600-pin ball grid array, it's implemented in a 0.18-µm CMOS process. While power consumption is rated at 6 W, its clock frequency is 200 MHz. Sampling now, the 3G-BP64 is scheduled for production toward the end of the year.
Meanwhile, Morphics is readying a version with 128 channels to double channel density. Besides supporting twice as many channels, it will integrate on-chip codecs and implement advanced receiver structures.
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