Just a couple of years ago, many designers struggled with bus and I/O speeds that continued to plod along while processors doubled their clock speeds every 12 to 18 months. Then, almost overnight, bus and I/O technology began to change. The speeds doubled, then doubled again. On top of that, new approaches like source-synchronous clocking—and the measurement challenges presented by the small data-valid windows of low-voltage differential signaling (LVDS)—have made measurement, verification, and validation more important than ever. Yet, the very same forces that bring such performance improvements also make the insertion of test equipment increasingly more intrusive.
The good news is that new tools and methodologies are available to minimize the impact on your design. However, careful planning for testing must now happen during the very initial stages of a design. It's no longer possible to build a prototype and then simply solder on some wires to connect a scope or logic analyzer. Your test methodology must be an integral part of your design plan.
Unfortunately, the techniques and tools that digital designers have used for years are no longer applicable. Today's designer wouldn't even think about designing a gigabit-per-second bus without extensive modeling and Spice simulations. Yet many of them continue to approach troubleshooting and debugging of these high-speed circuits with the same tools and methodologies implemented during the good old days of 4-MHz processors.
To achieve these breakthroughs in speed, such technologies as HyperTransport, InfiniBand, and RapidIO have adopted "new" electrical requirements like LVDS and replaced traditional multidrop buses with efficient point-to-point bus architectures. Suddenly, digital designers have been thrust from the comfortable world of ones and zeros into the high-frequency analog world. Those who attended their first class on fields and waves, and went screaming into the night, are being dragged back into the real-life classroom of transmission-line theory, reflections, and even S-parameters.
Because of the high-frequency effects and the new topologies of today's buses, designers need to more efficiently implement test equipment for determining signal integrity and data integrity. While simulation and emulation tools continue to mature and improve, the new bus technologies limit the usefulness of these tools.
For example, models are built over time from learning and observed behavior. When a new bus appears on the market, there's little information available to the majority of engineers. For the most part, leading-edge adopters of these technologies consider their knowledge intellectual property. They don't share this information until it becomes mainstream. So test tools, and the ability to employ them for debug and validation, are critical during early adoption.
With those old 4-MHz microprocessors—or the more recent USB 1.1 devices—a 100-MHz scope and any scope probe handy were more than enough. They could handle 1.5-Mbit/s or even 12-Mbit/s devices. Now, with 480-Mbit/s USB speeds, even a simple thing like an oscilloscope probe can dramatically impact your system's behavior.
How much more are your test-equipment measurement choices going to affect leading-edge systems, such as a HyperTransport link double-pumping data via a 1-GHz clock? Data capture is especially affected because of the reduction in setup-and-hold times. In fact, the emergence of new technologies has brought about new terminology. Setup-and-hold times are now passé terms. Now a high-speed data transfer is called a "data-valid window." This is a combination of setup, hold, and voltage swing.
Consider that in 1992, the Intel Pentium front-side bus (FSB) had a setup requirement of 5 ns and a voltage swing of 5 V. Today, the data-valid window for InfiniBand and RapidIO is 250 ps, with a differential voltage swing of 200 mV.
Compared to the 1992 Intel FSB, current InfiniBand specifications have a 20× reduction in the data-valid window and a 25× reduction in the voltage swing—a delta of 500. In other words, today's buses use only 0.2% of the energy that the 1992 Pentium FSB consumed.
Reprints
