A multiphase synchronous buck-converter architecture repartitions functions in silicon to create a scalable design suitable for many phases. Conceptually, the multiphase approach to building synchronous buck converters is scalable. The converter's load is distributed evenly across phase-shifted PWM channels and the associated output MOSFETs and inductors. That spreads the heat dissipation across several power-handling devices, while multiplying the switching frequency by the number of phases.
So in theory, the current output of a multiphase converter can be scaled up simply by increasing the number of phases. But in practice, multiphase designs aren't so easy to scale due to the ways that the pulse-width-modulation (PWM) controller, MOSFET gate drivers, and related functions have been integrated in silicon. Existing solutions for implementing multiphase converters accommodate two to four phases, yet they present difficulties when employing more phases.
This limitation will become an issue in powering future generations of microprocessors, which may require synchronous buck converters with six or more phases to generate the CPU's core voltage. For example, a pending CPU power specification calls for peak currents of up to 100 A at an on-the-fly programmable output voltage ranging from 0.875 to 1.6 V, selectable in 12.5-mV increments. The power supply must maintain the output voltage within ±25 mV, while providing a transient response on the order of 300 to 400 A/µs. Future CPU power requirements will be even more challenging.
Responding to these power needs, International Rectifier developed a new approach to multiphase converter design that overcomes the limitations of existing approaches. The company's Xphase technology repartitions the converter design into new functional blocks. These blocks can be configured easily to obtain anywhere from one to 16 phases.
Xphase represents both a new multiphase architecture and a family of devices. With its novel partitioning of converter functions and several innovations in circuit design, Xphase is designed to meet advanced CPU power requirements at the lowest possible solution cost. Nevertheless, design options within Xphase permit development of converter solutions optimized for efficiency and other parameters.
The Xphase architecture is based on novel controllers and "Phase" ICs. The Phase IC integrates all functions that are repeated in a multiphase design, including current share, PWM, phase timing, current sense, and dual gate driver. The controller contains those functions that occur only once in any multiphase design (Fig. 1 and Fig. 2).
Controller functions include 6-bit programmable voltage-identification (VID) circuitry, a PWM ramp oscillator, an error amplifier, bias voltage, and fault detection. The controller also contains the functions needed to meet the load line and transient response requirements of present and future microprocessors. The controller's oscillator frequency is programmable from 100 kHz to 1 MHz, and the output voltage may be programmed within 0.5% overall system accuracy.
With Xphase, the number of phases scales with the number of Phase ICs, and no silicon is wasted on unused functions. Contrast that with existing approaches in which the silicon is optimized for a fixed number of phases. If all phases aren't used, some silicon will sit idle, adding cost to the design. Moreover, existing approaches are difficult to scale both at the silicon and board levels.
For instance, one style of multiphase controller integrates the gate drivers on chip. This type of controller lowers cost by reducing component count. However, pc-board design gets more complex due to the difficulty in minimizing the trace lengths for the interconnects between the gate drivers and external MOSFETs. The parasitics associated with these traces can limit switching frequency. At the same time, the controller is subjected to the noise and heat generated by the gate drivers. Consequently, the single-chip controller plus gate drivers approach is limited to a maximum of about three phases.
Another style of multiphase controller eases board layout by separating the gate drivers from the controller IC, allowing implementation of three- or four-phase designs. But higher numbers of phases, which might be achieved by cascading controllers or using a more complex controller, makes layout even more complex. In part, this complexity results from having to route multiple current-sense signals back to the controller, adding parasitics to the current-sense circuits.
But whether gate drivers are integrated on the controller or not, the controller is optimized for a fixed number of phases. If any of the phases aren't used, the silicon won't be optimized for the design.
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