Standing as they do as the bridge between the digital and mixed-signal world of System-On-A-Chip (SOC) cores and the largely analog world of the circuit board, I/O cells are an increasingly difficult beast for designers to tame. Not only must I/Os typically comply with one of a rapidly expanding number of published electrical standards, but they must do so across a range of operating environments that may not have been considered by those who characterized the simulation models.
The fact that a published electrical specification exists for a given type of interface cell can make it seem as though using it is relatively simple. Yet that specification can never hope to anticipate all of the vagaries of that cell's real-world environment. Thus, SoC or ASIC designers attempting to coax their I/Os to simulate properly often find that the models work as expected within a given range of conditions but not outside it. If they expect their end product to see conditions at these design corners, what ensues is a long process of ascertaining what measurements must be taken, determining how to take them, and writing applicable Spice decks, a task that few designers are eager to take on.
With I/Os so critical to overall timing and power closure for ASICs, designers need more than ever to be able to accurately anticipate their real-world behavior. To that end, SiliconSmart IO from Silicon Metrics addresses the growing concerns of ASIC and SoC design teams regarding I/Os and their conformance with industry-standard specifications (Fig. 1). Not only does it automate the process of validating specification compliance, it does so with Spice-accurate characterization. If need be, the tool will automatically recharacterize the models to accurately reflect the I/Os' performance in the context of the overall design.
Consider that when I/Os are designed, they're usually intended for exclusive use in some limited set of electrical and environmental conditions. For example, a vendor might design the I/O to work with a pc board from a specific provider that might be willing to accommodate inadequacies or noncompliant aspects of the I/O cell by compensating in the board's design. If that vendor should later choose to sell that same I/O for use in new applications, those regions of noncompliance on the I/O's process voltage-temperature curve could necessitate a major redesign.
There's also the issue of the quality of characterization applied to cells by library vendors. To some consumers of off-the-shelf I/O intellectual property, characterization is lacking. "Do we really get good models from the library vendors?" asks Terry Hulett, vice president of engineering at Banderacom, a fabless semiconductor company in Austin, Texas. "I've convinced myself that no, we don't. Do I trust vendors to deliver me I/O libraries that are going to meet spec? To tell you the truth, no, I don't."
According to Rob Aitken, manager of ASIC design methodology at Agilent, the need for a tool like SiliconSmart IO is a matter of consistency, especially for those in the fabless IC world. "We get I/O intellectual property of all sorts from a bunch of different sources," Aitken says. "In order to produce working chips, it's necessary to have a consistent characterization methodology."
Preparing I/O models is typically a three-stage process. First, the models must be validated for compliance with standards across all expected operating environments. Next, they're characterized, meaning that the designers must determine an I/O's response to various environmental and electrical conditions. Lastly, models must be published in an error-free, accurate form.
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