FIFOs definitely play an integral and important role in a diverse range of challenging applications, such as storage-area networks (SANs) and networking routers. To keep pace with these fast-moving markets and meet new performance requirements, FIFO products continuously evolve. Today, the challenges that FIFO devices face include facilitating bandwidth and throughput of next-generation designs, while helping to drive down overall system costs.
Of course, the continuing push for higher-bandwidth data communication has created the need for FIFO devices with a higher data throughput. Traditionally, FIFO interfaces have been based on single-data-rate (SDR) parallel buses. However, this method has trouble keeping pace with applications that have higher throughputs. By moving to a double-data-rate (DDR) format, it's possible to leap to an entirely new level of performance.
DDR Approach: For years, designers have relied on FIFOs with SDR parallel bus architectures to provide crucial buffering between subsystems running at different clock rates. As overall system speeds rose in accordance with Moore's Law, designers helped FIFOs scale accordingly by increasing bus speeds or expanding bus widths. However, increasing the device speed meant that designers had to contend with augmented board-level noise and heat dissipation.
To circumvent the problems associated with increased clock speeds, some designers instead expanded the bus width (maintaining conventional clock speeds). By placing multiple devices in parallel, or increasing device bus widths, more data can flow through the system—effectively boosting the overall bandwidth.
This approach has its drawbacks too. The design requires substantially more data pins from the control ASICs or FPGAs, creating dozens more high-speed signals to route. Extra traces not only make it difficult to interface with other devices, but can also lead to higher noise margins and impedance. Additionally, I/O pins are a valuable commodity on ASICs and FPGAs. Designers are reluctant to increase pin counts due to a rise in cost that's proportional to the number of I/Os used.
Recently, a new memory architecture has emerged, designed to scale with the rising data rates found in current high-speed systems. By employing a DDR format, these devices address existing design issues while delivering an entirely new level of performance.
With a DDR device, data is clocked on the rising and falling edges of the respective read or write clock signals (Fig. 1). This effectively doubles the device's bandwidth without increasing the clock speed or bus width. For example, a 250-MHz DDR device operates at a performance equivalent to that of a 500-MHz SDR device.
In a DDR device, a write operation will occur on both the rising and falling edge of the write clock input (WCLK), if the write enable pin (WEN—) is active during the rising edge of the clock. The same is true on the read port, where a data-read operation will take place on both the rising and falling edges of the read clock input (RCLK), provided that the read enable pin (REN—) is active during the rising edge of the clock.
By using a 2n-prefetch architecture, where the internal data bus is twice the width of the external data bus, a DDR device can capture double the amount of data per clock cycle. As a result, a single write cycle will write two data words into memory, and one read cycle will fetch two data words from memory.
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