A modified form of synchronous DRAM technology, double-data-rate, fast-cycle random access memory (DDR FCRAM) is primarily focused at the networking market segment. Yet due to its high performance, it also suits such applications as graphics, gaming, and high-end set-top boxes.
DDR FCRAM's innovative architecture combines DRAM-type densities with random cycle times rivaling high-speed SRAMs. A multisourced technology supported by three major memory manufacturers, DDR FCRAM offers fast random cycle time and fast random access time, combined with a conventional DDR interface, to yield a cost-effective, high-bandwidth solution.
This article identifies the main differences and similarities between DDR FCRAM and DDR SDRAM devices. Additionally, it provides controller design guidelines for designers already using a standard DDR SDRAM interface to let them modify their existing designs for DDR FCRAM.
DDR FCRAM architectural enhancements have modified both the conventional DDR SDRAM core and its peripheral logic. This modification includes:
Core segmentation into smaller memory subarrays for lower power consumption.
Faster access times and peripheral logic to implement a three-stage row pipeline, enabling simultaneous execution of three commands.
Implementing hidden precharge further reduces the random cycle time (tRC). The three-stage row pipeline contains address-decoder, memory-array, and I/O buffer functions (Fig. 1). To illustrate this pipeline architecture, consider a Read operation: In conventional DRAM technologies, including DDR SDRAM, the memory location is first supplied. Then the data is read into the I/O buffer. Consequently, a conventional DDR SDRAM can't start executing the next address until the current Read Data output is complete.
In contrast, DDR FCRAM can accept a new address once the current address is latched in the decoder. A third address can also be specified once the data of the first address has moved from the memory array to the I/O buffer. This pipeline architecture makes DDR FCRAM ideal for networking applications that require short random cycle times and multibank accesses, such as packet buffering.
Similarities Exist: Even though DDR FCRAM's redesigned core concept offers significantly improved performance over DDR SDRAM, the two share several similar features. This makes it easy for designers to change their designs with minimum effort. The following attributes are common to both DDR FCRAM and DDR SDRAM:
TSOP 66-pin package
DDR clocking
Data strobe signal (DQS) clocking
four-bank organization
×8 and ×16 I/O organization
256-Mbit densities
two and four burst length
SSTL-2 2.5 V I/O
As mentioned earlier, the architecture of DDR FCRAM has been modified to deliver a faster random cycle time. DDR FCRAM has lower latencies and can handle up to three commands simultaneously. Figure 2 shows this concept. The timing diagram illustrates the differences between a conventional DDR SDRAM and DDR FCRAM. It also reveals the smaller initial latency (tRCD) of DDR FCRAM due to the integrated row address strobe (RAS) and column address strobe (CAS) in the command set. Besides minimizing the latencies, DDR FCRAM operates at a 200-MHz clock rate—delivering the speed needed by high-end networking applications.
Unlike DDR SDRAM, DDR FCRAM doesn't support page-mode operation. Instead, it automatically closes the row and precharges the bank. The device also has a significantly shorter random cycle time (25 ns versus 60 ns for DDR SDRAM).
Moreover, DDR FCRAM can seamlessly operate in the bank-interleave mode. Bus utilization of up to 80% in DDR FCRAM is significantly higher than other DDR DRAM technologies. This higher bus utilization makes the device a suitable replacement for expensive high-speed SRAM technologies.
Controller Considerations:Figures 3a and 3b show memory controller-to-DRAM and the microprocessor-to-memory controller interfaces for DDR SDRAM and DDR FCRAM, respectively. A DDR memory controller can be easily designed to accommodate both DDR SDRAM and DDR FCRAM. The —RAS, —CAS, and —WE pins are replaced by a function pin, FN, and two additional address pins, A13 and A14.
A comparison of functional truth tables for DDR SDRAM and DDR FCRAM command sets shows that the latter is much simpler (see the table). A standard DDR SDRAM has separate signals for command and address: The Active command is issued first, and the row address input takes place at the same clock edge. A Read/Write command and column address follows this. After a specified CAS latency, the Read or Write command is executed.
On the other hand, FCRAM has only two commands: First, an RDA or WRA command is issued, depending on if it's Read or Write (the state of —FN determines Read or Write), then the Lower Address Latch (LAL) command. The RDA and WRA specify the row, column, upper addresses (A0 to A14), and bank addresses, while the LAL completes the Read or Write operation by latching the lower addresses (A0 to A7). This broadside addressing (asymmetrical number of row/column addresses) lets FCRAM achieve faster random access and cycle times. Note that the above comparison is based on a 256-Mbit (×16) DRAM device.
There are other design considerations to address:
Signaling: To take full advantage of FCRAM, the high-speed bus must be able to pipeline addresses. Because a second address can be issued to the FCRAM before the production of the first requested data, an address pipeline must be implemented. DDR SDRAM does not require this.
For ASIC-embedded CPU and controller designs, the ECC, Arbiter, DMAC, memory controller (FCRAM and SRAM), and external-bus interface module must be designed with careful consideration of the following key guidelines for high-performance memory-controller design:
Activate the memory within one clock cycle.
Release the high-speed bus before the cycle's end to keep from holding the bus for an extra cycle.
Use an arbiter to stage bus usage between bus masters and allow priority selection.
Use burst-increment, decrement, and hold functions.
Keep the external load to a minimum (few FCRAMs located in close proximity to the ASIC).
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