[Design View / Design Solution]
DDR Memories Place Tough Demands On Voltage Regulators
Tighter dc regulation, higher output currents, and close tracking of the memory-bus and termination supply voltages make for happy memories.
The introduction of double-data-rate (DDR) memory has afforded a quantum leap in performance for commercially available desktop and portable computers. That's a step much warranted by the multigigahertz processor speeds found on today's motherboards.
With a 2.6-GHz CPU, typical 100-Mbit/s SDRAM would be a throughput bottleneck. Brute-force speed increases in standard SDRAM create power-dissipation, noise-margin, transmission-line, and cost problems. Adding DDR memory doubles the data-transfer rate without doubling the clock rate, avoiding pc-board design and layout complexity. However, it requires that the DDR regulators have tighter dc regulation, higher currents, and close tracking for both the VTT (termination supply voltage) and VDD (memory bus supply voltage) regulators.
For the PC2100 device discussed in the article, a new approach to data transmission and line termination was adopted so that the data lines can switch at twice their previous speeds over the same pc-board traces. The DDR266 device employed has a clock frequency of 133 MHz and a peak data transfer of 266 Mbits/s. That's 2.1 Gbytes/s (PC2100) for a 64-bit wide bus over the same pc-board traces of the PC133 (266 × 8 = 2100).
Power considerations when moving from single-data-rate (SDR) to DDR memory are discussed. Newer DDR2-type memories should bring considerable power savings over the current DDR1 version due to lower-voltage rails.
Other key considerations are dc-dc converter compliance with DDR power and bus accuracy, along with meeting timing and sequencing guidelines. The regulator comes into play here.
HIGHLIGHTS:
Noise-Margin Calculations
Termination Resistors for DDR are selected based on factors such as worst-case drive source resistance (RON) and length of pc-board trace.
DDR Power Considerations
Moving from single-data-rate (SDR) memory to DDR brings new power requirements to VDOQ as well as the I/Os. DDR2-type memory (VDOQ = 1.8 V) consumes 30% less power than DDR1 (VDOQ = 2.5 V) versions.
Dual Channels
The newer dual-channel data-bus architecture (DDR2) doubles the number of data bits by using two 64-bit data buses. The bus basically doubles the active current associated with DDR DRAMs.
Integrated DDR Controllers
To take full advantage of the DDR memory, the dc-dc converters must comply with the DDR power and bus-accuracy requirements. IAPC (instantly available PC) specifications for timing and sequencing further complicate matters. Thus a regulator like the SC2616, which is detailed in the article, is crucial in this case.
MR. KOOHIAN, I read your article, and it seems very good and intersting. Good luck.
asali -October 25, 2003
Great Article(s) (I also read the article on Flyback Converter). Thanks a lot for a great job, well done!
Regards;
mehdi
Mehdi -May 08, 2003
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