In the past decade, IEEE 1149.1, or "JTAG," has become one of the mainstream design-for-testability (DFT) techniques. It has grown from an often discussed but seldom used concept into a primary test strategy for many new designs.
Boundary scan, an element of the JTAG specification, is enjoying a rise in popularity due to many factors. One of them is the increasing use of the ball-grid-array (BGA) and other high-density interconnect packages. Board designers have adopted boundary scan to provide test coverage for circuit nets that aren't accessible by conventional test probing.
Telecom and networking companies are routinely developing boards with net counts above 5000. That's the practical limit of commercial ATE systems available today. Boundary scan offers unlimited virtual test channels.
Also, in-system programmable (ISP) devices often use the test access port (TAP) defined by the 1149.1 standard. It gives system designers a built-in port to implement in-system programming.
Today, every major telecom, network, aerospace/defense, and VLSI device manufacturer uses boundary scan in their designs. This strategy offers high test coverage, reduces life cycle costs, and shortens time-to-market.
Designers incorporating boundary scan in ASIC/VLSI designs find a variety of tools for implementing the infrastructure in a relatively painless manner. For circuit board designers, though, there are fewer tools available and more opportunities to make mistakes. To avoid some obstacles, it's important to examine some of the common pitfalls made by boundary-scan pioneers, and note techniques for optimization in board designs.
The terms "boundary scan" and "scan" are used interchangeably to refer to the technique described in IEEE 1149.1. While there are many other types of scan-based design-for-test methodologies, the most prevalent today is the 1149.1 version. The term "scan device" refers to any device that incorporates boundary scan in the device's architecture.
Basic Mistakes To Avoid
Common mistakes on board designs result when designers are unaware of boundary scan's benefits and they violate the testability rules. Some examples of these blunders are TAP signals tied to VCC or GND, the lack of test pads provided for TAP signals, TAP pins either not bussed or else improperly bussed, and the failure to provide boundary-scan description language (BSDL) files.
In the first case , the designer has mistakenly tied the TAP pins—test data in (TDI), test data out (TDO), test mode select (TMS), and test clock (TCK)—to either a power rail or a ground bus (Fig. 1a). This mistake often occurs when there's a blanket design rule like "tie all unused pins to power/GND".
Because the TAP pins are tied directly to power or ground, there's no way to apply scan test patterns to the device. To prevent this, never tie unused signal pins to power or ground. If you're not sure about a pin's function, leave it alone, or tie it to power or ground via a resistor (Fig. 1b).
Another problem arises when there's no method for physically accessing the TAP pins. This is the case in any surface-mount package outline where the designer hasn't provided a test pad or test connector pin. Then, there's no convenient way to connect test stimulus/response hardware for conducting boundary-scan tests. To perform boundary-scan tests, it's necessary to provide a means for physical electrical access to the first TDI and last TDO pins in the scan chain, and TMS and TCK for the entire chain (Fig. 2).
Many of boundary scan's benefits can be derived even if only a single device in the board design has scan capability. The real power and attractiveness of boundary scan, though, is obtained when multiple scan devices on the board are connected in a single-scan chain (Fig. 2, again, and Fig. 3).
There are many reasons why this connection is the best. Only a single TDI and TDO net need a test pad/test connector. This will save circuit-board real estate, and reduce the number of tester channels required to support scan testing. Commercially available test-pattern generators are generally optimized for developing test patterns and diagnostic databases for a single-scan-chain topology. Using a single chain allows all of the nets associated with boundary-scan registers to update in parallel. This will help avoid glitches.
In spite of the single-scan chain's benefits, a few cases, like very-large board designs, might require multiple-chains. The sheer distance between devices and board density may not allow the TAP signals to connect by a single chain without violating other design considerations, such as noise coupling.
Another instance is a board in which the designer selected a multidrop technique. That will partition the board into multiple sections, with the scan chains isolated to each section. This is an advanced method, practiced by very skilled designers with vast experience in DFT techniques.
Cases where mixed logic levels preclude tying all of the devices into a single chain also necessitate multiple scan chains. This generally only happens in designs where a negative-voltage logic, such as emitter-coupled logic, is used with positive-voltage logic (i.e., TTL).
Circuits also become difficult if not impossible to use for boundary-scan testing if the board designer connected the scan devices incorrectly (Fig. 4). Common versions of this problem include all TDI signals tied together, rather than in a daisy chain of TDO to TDI, and TCK pins connected to an existing on-board clock signal source. To prevent these problems, connect the devices as shown in Figure 3.
Boundary scan is a powerful DFT technique. Still, if the BSDL files defining the implementation of scan registers for a given device aren't provided to those responsible for test generation and implementation, it cannot be used.
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