Semiconductor devices can modify their behaviors based on the parameters written to the internal registers, or the control-voltage levels provided to the input pins. Pin count is sometimes a limiting factor, though, and many designers prefer to utilize the register approach. There are several ways to write the parameters in registers. Some of the most common methods include:
- The control register located at the dedicated address inside the device. This is common among memory devices, such as flash memory. To write the parameters, the host addresses the specific location and supplies the parameter value to this register.
- The chip select specific to the control registers. This type of device provides a dedicated line that, when asserted, accesses the read/write operation to the control registers.
- A dedicated bus to write to the control registers. Dedicated pins are assigned, which a host uses to write the parameters to the device.
What is MDIO?
Management Data Input/Output, or MDIO, is a standard-driven, dedicated-bus approach that's specified in IEEE RFC802.3. The MDIO interface is implemented by two pins, an MDIO pin and a Management Data Clock (MDC) pin. The IEEE RFC802.3 specification defines MDIO in Chapter 22, and Chapter 45 further defines the 802.3ae specification. This article discusses both sections of the specification in that order.
In Chapter 22, the MDIO interface is defined in relationship to the accessing and modification of various registers within physical-layer (PHY) devices, and how they relate to connecting to media access controllers (MACs) in 1- and 10-Gbit/s Ethernet solutions. See Figure 1 for an example of the interface.
One MDIO interface can access up to 32 registers, in 32 different devices. A device driving an MDIO bus is called a station management entity (STA), and the device being managed by the STA is called the MDIO Manageable Device (MMD). The STA drives the MDC line. It initiates a command using an MDIO frame and provides the target register address. During a write command, the STA also provides the data. In the case of a read command, the MMD takes over the bus and supplies the STA with the data. Figure 2a illustrates the MDIO frame format, while Figure 2 defines the terminology. Figure 3 shows both the read and write frames.
Chapter 45 specifies the extension to the MDIO, where the following changes are made:
- Capability added to address more registers--up to 65,536 registers in each device.
- More OP-code and ST-code added, which specify the extension (two additional OP-codes and ST-code from 01 to 00).
- Modification of electrical interfaces from the original specification. The earlier specification stated 5- and 3.3-V signal levels. The extension includes signal levels to 1.5 V
The extension specification also allows one STA to drive 32 ports of 32 devices. To access the registers, the STA issues a read or write command to the given addressed MMD and register in that MMD. Where a register isn't implemented, a write command to the unimplemented register or bits doesn't affect the MMD's operation. A read command to the unimplemented bit or register returns a value of 0.
The PHY specification: MDIO/MDC pins are implemented using 5- or 3.3-V TTL signals. For the extension, "0- to 1.5-V" signal logic is specified.
MDIO is a bidirectional signal sourced by the host (STA), or by the slave (MMD). The standard specifies timing distinction, such that when the STA sources the MDIO signal, it provides a minimum of 10-ns setup and hold time with respect to the MDC signal. If the MMD is supplying the MDIO signal, the specification allows the clock-to-data delay to be a minimum of 0 ns and a maximum of 300 ns. This is an important factor in the ease of implementing the interface. However, it puts a restriction on the bus bandwidth.
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