While DRAM memory cells have continually shrunk, scaling has, to some extent, reached its limit. Also, the mixed analog and digital technologies used to implement DRAM storage cells, sense amplifiers, and control logic have forced designers to compromise on some performance issues when co-integrating analog and digital technologies.
But now, a radical reorganization of DRAM circuitry that leverages wafer-stacking technology promises higher-density and lower-cost memories that deliver top-notch performance. This use of wafer-stacking technology and the revamping of the memory architecture and circuitry were devised by Tachyon Semiconductor Corp., a startup based in Naperville, Ill.
"To achieve the best digital and analog performance," explains Robert Patti, Tachyon's CTO and one of its founders, "we drastically revised the way a DRAM is architected, separating the digital circuitry from the analog, placing digital circuitry on one wafer and analog circuitry on another."
Separating them optimizes each circuit for the best performance possible. SDRAM access times of 8/4/4/4 ns (initial and three subsequent accesses) and densities of 1 Gbit/package will be possible in the first generation of memories built using the stacking technology.
In contrast, today's SDRAMs offer access times of 45/6/6/6 ns and top capacities of 256 Mbits/chip. Stacked SDRAMs can deliver high-speed accesses competitive with the best SRAMs while consuming little power, occupying less board space than standard SDRAMs or SRAMs, and costing less (estimated at about half the per-megabyte cost of SDRAMs).
Getting high capacity at low cost meant including built-in self-test (BIST) and repair circuitry to find bad cells, map them out of the array, and map in replacement good cells. Tachyon's proprietary technology, BiStar, was used to accomplish this task. BIST and repair circuitry employ an internal controller that performs a very fine-grained mapping of all the good bits at power-up. The circuitry can also work in the background to continually test the bits and replace defective ones. Separating logic and the highly interconnected memory cells makes cell-by-cell mapping possible.
BiStar technology includes error-checking and correction logic to catch transient errors due to alpha-particle upsets or marginally good cells. A memory stack can tolerate well over 10,000 bit errors per device. BiStar stacks can provide a manufacturing yield of 97%, keeping per-unit costs well below those of standard SDRAMs.
The wafer-stacking technology was developed by Tachyon but leverages several patents the company licensed from other industry sources. The process starts by creating two base wafers (Fig. 1). One holds optimized digital control logic and sense amplifiers, which are covered with an oxide insulator layer. The insulator layer is patterned to create contact openings. Copper is deposited, filling the contact holes and covering the oxide. That copper layer is then patterned before bonding to the second wafer.
Arrays of memory storage cells are formed on the surface of the second wafer. Intermixed with the memory arrays is the company's proprietary redundancy interconnect circuitry and self-repair structures, which greatly improve circuit yield and allow for in-system repair. This ensures that systems can remain online even if some memory bits fail.
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