As always, the 40th Design Automation Conference (DAC) in Anaheim (June 2-6) will have something for everyone concerned with EDA. The latest and greatest tools and methodologies will be displayed either on the show floor or in the sprawling labyrinth of high-walled demo suites. In addition, there's a full slate of technical sessions, panels, tutorials, and workshops to bring you up to date on the state of the art in design automation (see "Scanning The Sessions," p. 49). Also, the innumerable dinners, parties, and assorted gatherings provide ample opportunity to peer into the minds of the EDA industry's leading lights in an effort to discern key trends.
But as always, the tools are the stars of the show. DAC has long been the premier venue for EDA product rollouts. This year, attendees will see numerous announcements related to all areas of EDA: system-level design, intellectual-property (IP) and reuse/integration issues, pc-board tools, logic design, physical design, and analysis and verification.
A move up in abstraction has been in the offing for logical design for some time. We'll see some new developments in system-level design at the show, as tool flows continue to take shape for algorithmic design exploration.
According to Guy Moshe, president and CEO of Summit Design, C/C++ is the "common denominator" bridging SystemC and SystemVerilog, two of the leading candidates for system-level language supremacy. "C/C++ delivers the language abstraction with all its associated benefits, and the linkage to software with all the associated legacy and popularity," Moshe says.
For system-level design to work, there must be tools that provide viable hardware models to software developers early in the design cycle. Tenison EDA will show version 2 of its VTOC virtual silicon modeling tool, which converts Verilog code into C, C++, or SystemC. A new command-line feature gives users flexibility to build models of partial and incomplete designs, permitting coding of software or firmware even earlier in the development cycle.
Celoxica will show version 2 of its DK design suite, which performs what's called "software-compiled" system design. The tool uses high-level design languages to drive design verification and implementation. Also at DAC, Celoxica will demonstrate numerous applications and announce significant relationships with several IC companies, including ARM Ltd.
Although interest in SystemC is rising, many designers still require training in its application. Forte Design Systems will demonstrate online SystemC training, which will be offered free of charge from its Web site, www.forteds.com.
Another key to the viability of system-level design is a view into all aspects of design from the architectural level. In the latest version of its system-level power-estimation tool, ChipVision will include a new SystemC front end to supplement existing C/C++ support as well as source-code reverse-analysis capabilities. Called Orinoco 2003.1, the tool features a new scheduling graph that gives designers a view of their system architecture. Pricing is $120,000 for a three-year license.
System-level design has lagged somewhat in the practical realm. This is not due to a lack of design tools but rather the lack of a true system-level verification methodology in which hardware and software are verified concurrently. At DAC, Axis Systems will introduce such a methodology, one that can bind pre-built design and verification components together to raise abstraction levels from the front end to the back end of the cycle.
Meanwhile, CoWare will show its ConvergenSC product family, touted as the first system-level tools to use a common infrastructure for both design and verification. Built expressly for SystemC, ConvergenSC will launch its first product, System Designer, at the show. It provides high-speed simulation, architecture analysis, and design implementation on a single SystemC-based infrastructure. Capabilities include creation of SystemC transactional prototype models for systems-on-a-chip (SoCs) containing multiple processors, complex buses, memories, custom logic, and software.
System Designer's SystemC simulation architecture runs five times faster than the Open SystemC Initiative's reference simulator. Thanks to the tool's analysis capabilities, it can create optimal design architectures, including Bus Views, Memory Views, and Embedded Processor Views (Fig. 1). Transactional bus simulators are available to provide baseline configurations of popular bus standards like ARM's AMBA. Also, third-party tool support is available from Novas, Cadence, and Synopsys. Pricing starts at $105,000 for a three-year license.
In the multisim, how can I see the current waveform,across any component? Please give a suggestion.
Manjula Bai -September 24, 2004
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