Circuit designers face many electrostatic-discharge (ESD) concerns in their quest for a functional and reliable product. Moreover, the evolution of the electronics marketplace toward higher data throughput and faster signal speeds adds to this complexity. Basically, ESD protection falls into two categories: protection during manufacturing, and protection in the "real-world" environment.
On-chip transient-voltage-suppression (TVS) structures are designed to increase chip yields in foundry and board-manufacturing environments. They typically follow such standards as the Charged Device Model (CDM), the Machine Model (MM), and the Human Body Model, MIL-STD HBM. But the severity of ESD in the "real-world" environment is much higher.
Everyday users of electronic products (cell phones, PDAs, laptop computers, etc.) introduce a more severe level of ESD into those products. These ESD transients are typified in the IEC 61000-4-2 test methodology. It's important to remember that survival through the manufacturing process does not guarantee survival in the hands of the end-user. "Supplemental" ESD protection, like ESD suppressors, may be necessary. This article focuses on critical selection criteria of ESD suppressors and provides recommendations and supporting data for guiding optimal ESD protection at the board level.
Designers need to understand not only the suppression characteristics of ESD protectors, but also their package characteristics. It's extremely important that stray characteristics, such as capacitance, are understood in order to take them into consideration during the board design. In other words, make sure the ESD suppressor is a good fit with the circuit parameters (data rates, leakage current, and so on).
Optimal placement of ESD suppressors begins at the location of ESD penetration into the system. This tactic reduces the ESD voltage and current initially experienced by the circuit and attenuates the ESD pulse that propagates past the ESD suppressor. Design as much practical space as possible between the ESD suppressor and the protected chip.
Placing an ESD suppressor too far away from the line it's protecting can reduce its effectiveness. The board trace inductance can cause an additional amount of voltage, or "overshoot," on the chip. To avoid this, install the ESD suppressor as close to the protected line as possible. The bottom line is that selecting an ESD "solution" is no longer as simple as choosing a suppressor that's rated for the operating voltage of the circuit. An effective solution now takes into account the layout of the circuit board, as well as the nonsuppression electrical characteristics of the ESD suppression devices. Before delving further into the specifics of ESD protection, it's helpful to review some fundamentals.
ESD basics: A topic of particular concern to designers is the inadvertent damage done by the end users of electronic products. Normal day-to-day activities can cause people to build up static electricity, which might later be transferred to objects like file cabinets, doors, and electronic devices. As a person walks across a carpeted floor, a transfer of charge occurs. Similarly, the act of sliding out of an office chair can cause a transfer between the chair and its occupant. This effect, called triboelectric charging, happens any time two dissimilar materials come into contact and then separate. The subsequent transfer of electrical charge to an object at lower electrical potential is referred to as electrostatic discharge.
The issue at hand for the design, quality, and reliability communities is the effect of static electricity transference on their electronic products. If the ESD pulse finds its way into the electronic devices, the circuitry inside can be physically damaged. The ESD Association has estimated the average loss of products due to user-generated ESD at 27% to 33%. Whether the product loss occurs at the user level or during the manufacturing process, ESD can lower product reliability and company profit. To help reduce losses due to ESD, chip manufacturers can incorporate TVS structures into their integrated circuitry dies. This will make them more robust and help to increase yields in chip-foundry and board-manufacturing processes.
The big problem occurs when the electronic product transfers from the manufacturing environment to actual daily use. The level of ESD the end user can generate and introduce to the electronic device is much more severe than the level found in the controlled manufacturing environment. This means that a design that had high yields during manufacturing can experience higher losses in the field. Consequently, the focus of ESD protection has shifted from chip hardening to system hardening.
ESD suppression: The ability of an IC or ASIC to survive the manufacturing process doesn't guarantee that it will survive "real world" usage. What can be done to improve the survivability, or reliability, of your design? Currently, numerous protection options are available to the designer. These in-clude isolation circuits, filtering circuits, and suppression components, such as multilayer varistors, silicon diodes, and the newly introduced polymer-based suppressors.
Suppression components protect the circuit by clamping the ESD voltage to a level that the circuit can survive. Connected in parallel with the signal lines, the suppressors clamp the ESD voltage and shunt the majority of the ESD current away from the data line, and the protected chip, to the appropriate reference. Typical references are the power rail and chassis ground.
While these approaches can all en-hance an electronic device's ESD survivability, there are inherent characteristics to consider during the selection process. Obvious characteristics include size, pin out, pad layout, and leakage current. But as the need for circuits to provide higher informational throughput increases, another characteristic becomes very important—capacitance.
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