Scaling analog circuits and data converters in CMOS has always been a daunting task for designers. But those hurdles get taller as developers begin migrating toward design rules of 0.25 µm and below for lowering power consumption, size, and the cost of these complex chips. Subsequently, achieving the dynamic range, speed, bandwidth, and noise performance at sub-2-V operation poses many design challenges, as researchers push technology to its limits. Several ISSCC papers on this front reveal techniques to accomplish new goals at lower supply voltages by using advanced deep-submicron CMOS processes.
For the first time, Nyquist analog-to-digital converters (ADCs) have broken past speed records to sample above 1 Gsample/s. Oversampling ADCs also have pushed the low-power benchmark for GSM/EDGE digitizers down to 5 mW, while the search for a universal ADC has resulted in an adaptable architecture that covers 6 to 15 bits of resolution with bandwidths from 1 Hz to 10 MHz. Furthermore, the higher speed mania is pushing voltage-controlled oscillators (VCOs) toward the 50-GHz mark. The reported CMOS VCO topology operates both at high frequency and with a low voltage.
To serve leading-edge disk-drive read channels and high-speed Ethernet applications, researchers at UCLA's Electrical Engineering Department have developed a 6-bit CMOS ADC that exploits array averaging in a flash architecture to sample at 1.3 Gsamples/s (paper 8.1). The averaging technique reduces the effect of offsets, allowing the use of small transistors, and it provides higher speeds. This scheme implements averaging in both preamplifier stages and comparators to lower the input-referred offset from 8.1 to 2.8 mV (Fig. 1).
The ADC has a high-speed ROM-based encoder to convert thermometer code at the output of the latch array to quasi-Gray code, and then to binary code. A wideband track-and-hold amplifier precedes the flash quantizer to achieve better than a 5.5 effective number of bits (ENOB) for input frequencies of up to 600 MHz at a sampling rate of 1 Gsample/s. For 650-MHz inputs and 5 effective bits, the ADC can sample at 1.3 Gsamples/s.
The ADC consumes 500 mW at 3.3 V and a 1-GHz conversion rate (not including the output buffers). Power consumption goes to 545 mW as the conversion frequency is increased to 1.3 Gsamples/s. Integral and differential nonlinearity (INL and DNL) is below ±0.3 LSB at a 1-Gsample/s conversion. The dynamic performance at this rate is around 35 dB at a Nyquist input frequency of 500 MHz. The device occupies 0.8 mm2 of the active area in a 0.35-µm four-metal CMOS process.
Researchers at Philips Semiconductors have additionally achieved similar performance for a 6-bit flash CMOS ADC, but they use less silicon and power (paper 8.2). The company demonstrated a maximum sample rate of 1.1 Gsamples/s by combining interpolation and averaging techniques, along with a distributed sample-and-hold circuit.
This converter is a straightforward 6-bit full-flash ADC that consists of a resistive ladder with 63 taps followed by 63 comparators. The output from the comparator array feeds an encoder that converts thermometer code into 6-bit binary code. Unlike the UCLA approach, Philips' researchers used a distributed sample-and-hold stage, consisting of 15 differential circuits to simplify the design. According to the paper, each sample-and-hold circuit must be linear for only a small signal range as opposed to being linear over the entire input bandwidth. Implemented in 0.35-µm CMOS, the ADC occupies only 0.35 mm2 of silicon and consumes 300 mW at 3.3 V and a 900-Msample/s conversion rate. At this conversion rate, ENOB is 5 bits up to a 450-MHz input.
Other highlights of Session 8 included a 100-MHz pipelined ADC that dissipates only 180 mW from 1.8 V, and a 14-bit multistage pipelined 75-Msample/s ADC with a spurious-free dynamic range (SFDR) of 85 dB at the Nyquist input frequency.
In paper 8.3, designers from Texas Instruments Inc., Dallas, address sub-2-V issues for fast 10-bit pipelined CMOS ADCs. Here, the 100-MHz 10-bit ADC employs 0.5 bits of redundancy per stage to allow large offsets. In addition, to achieve high open-loop gain for each residue amplifier, it uses a two-stage op amp with Miller compensation. In short, it employs a traditional 9-stage architecture, with each stage resolving 1.5 bits. A sample-and-hold circuit is added upfront for better dynamic linearity for high-frequency input signals. To generate the final digital code, the 10-bit ADC uses digital error-correction circuitry (Fig. 2).
The device was fabricated in a 0.18-µm single-polysilicon standard digital CMOS process. At 1.8 V and 180 mW of maximum power consumption, it sets a new benchmark for any 10-bit 100-Msample/s CMOS ADC. The IC has 9.4 ENOBs for a 50-MHz input at the full sampling rate.
Using a 4-bit flash and a 4-bit residue stage, followed by eight 1.5-bit pipeline stages and a 3-bit flash, a 14-bit 0.35-µm polysilicon triple-metal CMOS ADC from Analog Devices Inc., Wilmington, Mass., flaunts 85 dB of SFDR without calibration or trimming, and an unprecendented conversion speed of 75 Msamples/s at 14 bits of resolution (paper 8.5). While the ADC uses digital correction to compensate for comparator errors, the 4-bit residue stage improves linearity and cuts power consumption in subsequent stages.
Because the capacitor size in this switched-capacitor pipeline design is determined by the noise and matching requirements, stage-1's input capacitor was kept to no more than 4 pF to meet the 70-dB noise budget. Together with 4-bit segmentation and careful layout, this capacitor sizing provides 14-bit DNL performance. The ADC's 2.7-V minimum supply mandates a small full-scale input range of 2 V p-p. Power consumption, including the core and output drivers, is 340 mW at 3 V.
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